fix setvl. not setting CR0 properly

diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn
index 648f43d8e393fc40360fa94b7c0539b33f5f479e..d3b318ee15d0e7f50d74e29dce62b74c205c8f08 100644 (file)
--- a/openpower/isa/simplev.mdwn
+++ b/openpower/isa/simplev.mdwn
@@ -30,6 +30,10 @@ Pseudo-code:
         step <- SVSTATE_NEXT(SVi, 0b0)
         if _RT != 0 then
            GPR(_RT) <- [0]*57 || step
+        if Rc = 1 then
+            if step = 0 then c <- 0b001
+            else c <- 0b010
+            CR[32:35] <- c || XER[SO]
     else
         VLimm <- SVi + 1
         # set or get MVL
@@ -37,7 +41,9 @@ Pseudo-code:
         else           MVL <- SVSTATE[0:6]
         # set or get VL
         if vs = 0                then VL <- SVSTATE[7:13]
-        else if _RA != 0         then VL <- (RA)[57:63]
+        else if _RA != 0         then
+            if (RA) >u 0b1111111 then VL <- 0b1111111
+            else VL <- (RA)[57:63]
         else if _RT = 0          then VL <- VLimm[0:6]
         else if CTR >u 0b1111111 then VL <- 0b1111111
         else                          VL <- CTR[57:63]
@@ -52,6 +58,10 @@ Pseudo-code:
             # set requested Vertical-First mode, clear persist
             SVSTATE[63] <- vf
             SVSTATE[62] <- 0b0
+        if Rc = 1 then
+            if VL = 0 then c <- 0b001
+            else c <- 0b010
+            CR[32:35] <- c || XER[SO]
 
 Special Registers Altered:
 

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index b5d9f5a5955601a0202fb2d4191310bad6432180..16da237812afc0024e3387bb0ab9ab430cac9e7a 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1435,7 +1435,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
         if not self.is_svp64_mode or not pred_dst_zero:
             if hasattr(self.dec2.e.do, "rc"):
                 rc_en = yield self.dec2.e.do.rc.rc
-        if rc_en and ins_name not in ['svstep']:
+        if rc_en and ins_name not in ['svstep', 'setvl']:
             regnum, is_vec = yield from get_pdecode_cr_out(self.dec2, "CR0")
             self.handle_comparison(results, regnum)