Enforce explicit src/dest masks on CR twin-predication

diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py
index 37d5abee9cb700289eeac1b31a226a6c6963e02b..a28f94cd594952c8558c5f59e62075c3c4707087 100644 (file)
--- a/src/soc/sv/trans/svp64.py
+++ b/src/soc/sv/trans/svp64.py
@@ -491,6 +491,15 @@ class SVP64Asm:
                         "cannot have both source-mask and predicate mask"
                     assert not has_pmask,\
                         "cannot have both dest-mask and predicate mask"
+                # since the default is INT predication (ALWAYS), if you
+                # specify one CR mask, you must specify both, to avoid
+                # mixing INT and CR reg types
+                if has_pmask and pmmode == 1:
+                    assert has_smask, \
+                        "need explicit source-mask in CR twin predication"
+                if has_smask and smmode == 1:
+                    assert has_pmask, \
+                        "need explicit dest-mask in CR twin predication"
 
             # sanity-check that 2Pred mask is same mode
             if (has_pmask and has_smask) or mask_m_specified: