more cases of Elaboratable

diff --git a/src/add/fpadd/add0.py b/src/add/fpadd/add0.py
index 7d84b74cfde77d347f962884c97803245f225c4e..76790fe22bbd4d48220e98b78d694b8ef2567180 100644 (file)
--- a/src/add/fpadd/add0.py
+++ b/src/add/fpadd/add0.py
@@ -2,7 +2,7 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Cat 
+from nmigen import Module, Signal, Cat, Elaboratable
 from nmigen.cli import main, verilog
 
 from fpbase import FPNumBase
@@ -24,7 +24,7 @@ class FPAddStage0Data:
                 self.tot.eq(i.tot), self.mid.eq(i.mid)]
 
 
-class FPAddStage0Mod:
+class FPAddStage0Mod(Elaboratable):
 
     def __init__(self, width, id_wid):
         self.width = width

diff --git a/src/add/fpadd/add1.py b/src/add/fpadd/add1.py
index 08c27b8e0e3f0c8e3b080271f7ce90ace4aafe2e..679f5176d2d9227c41637d9fb9db2d6c08c6845d 100644 (file)
--- a/src/add/fpadd/add1.py
+++ b/src/add/fpadd/add1.py
@@ -2,7 +2,7 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal
+from nmigen import Module, Signal, Elaboratable
 from nmigen.cli import main, verilog
 from math import log
 
@@ -11,7 +11,7 @@ from fpcommon.postcalc import FPAddStage1Data
 from fpadd.add0 import FPAddStage0Data
 
 
-class FPAddStage1Mod(FPState):
+class FPAddStage1Mod(FPState, Elaboratable):
     """ Second stage of add: preparation for normalisation.
         detects when tot sum is too big (tot[27] is kinda a carry bit)
     """

diff --git a/src/add/fpbase.py b/src/add/fpbase.py
index 66cc8c0e37334a2fcbc58d233836aa8acf76ac6b..8f5094c16ae9b416b2970e603289da92a88f8d84 100644 (file)
--- a/src/add/fpbase.py
+++ b/src/add/fpbase.py
@@ -2,7 +2,7 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Signal, Cat, Const, Mux, Module
+from nmigen import Signal, Cat, Const, Mux, Module, Elaboratable
 from math import log
 from operator import or_
 from functools import reduce
@@ -60,7 +60,7 @@ class MultiShift:
         return res
 
 
-class FPNumBase:
+class FPNumBase: #(Elaboratable):
     """ Floating-point Base Number Class
     """
     def __init__(self, width, m_extra=True):
@@ -214,7 +214,7 @@ class FPNumOut(FPNumBase):
         return self.create2(s, self.N127, self.mzero)
 
 
-class MultiShiftRMerge:
+class MultiShiftRMerge(Elaboratable):
     """ shifts down (right) and merges lower bits into m[0].
         m[0] is the "sticky" bit, basically
     """
@@ -257,7 +257,7 @@ class MultiShiftRMerge:
         return m
 
 
-class FPNumShift(FPNumBase):
+class FPNumShift(FPNumBase, Elaboratable):
     """ Floating-point Number Class for shifting
     """
     def __init__(self, mainm, op, inv, width, m_extra=True):
@@ -464,7 +464,7 @@ class FPNumIn(FPNumBase):
                 self.m.eq(sm.lshift(self.m, maxslen))
                ]
 
-class Trigger:
+class Trigger(Elaboratable):
     def __init__(self):
 
         self.stb = Signal(reset=0)
@@ -537,7 +537,7 @@ class FPOpOut(NextControl):
                ]
 
 
-class Overflow:
+class Overflow(Elaboratable):
     def __init__(self):
         self.guard = Signal(reset_less=True)     # tot[2]
         self.round_bit = Signal(reset_less=True) # tot[1]

diff --git a/src/add/fpcommon/corrections.py b/src/add/fpcommon/corrections.py
index 166610c3c77d364bfa8d05fb72b6bcb3f1402c39..ce9ba3cd190b7c21cf46b2316396af7f0096a6a4 100644 (file)
--- a/src/add/fpcommon/corrections.py
+++ b/src/add/fpcommon/corrections.py
@@ -2,13 +2,13 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module
+from nmigen import Module, Elaboratable
 from nmigen.cli import main, verilog
 from fpbase import FPState
 from fpcommon.roundz import FPRoundData
 
 
-class FPCorrectionsMod:
+class FPCorrectionsMod(Elaboratable):
 
     def __init__(self, width, id_wid):
         self.width = width

diff --git a/src/add/fpcommon/getop.py b/src/add/fpcommon/getop.py
index 5b500522bbf3be530f5a32c0a24d68c7834b4b5f..96a03c3e98d691034774f39ca5859adb288531f1 100644 (file)
--- a/src/add/fpcommon/getop.py
+++ b/src/add/fpcommon/getop.py
@@ -2,7 +2,7 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Cat, Mux, Array, Const
+from nmigen import Module, Signal, Cat, Mux, Array, Const, Elaboratable
 from nmigen.lib.coding import PriorityEncoder
 from nmigen.cli import main, verilog
 from math import log
@@ -17,7 +17,7 @@ from multipipe import PriorityCombMuxInPipe
 from fpbase import FPState
 
 
-class FPGetOpMod:
+class FPGetOpMod(Elaboratable):
     def __init__(self, width):
         self.in_op = FPOpIn(width)
         self.out_op = Signal(width)

diff --git a/src/add/fpcommon/normtopack.py b/src/add/fpcommon/normtopack.py
index 14814669c857a4d9d9579c725ccac9d742d68d29..87d08125f8723738db9177b4275f2c542b4967d2 100644 (file)
--- a/src/add/fpcommon/normtopack.py
+++ b/src/add/fpcommon/normtopack.py
@@ -37,7 +37,8 @@ class FPNormToPack(FPState, SimpleHandshake):
         rmod = FPRoundMod(self.width, self.id_wid)
         cmod = FPCorrectionsMod(self.width, self.id_wid)
         pmod = FPPackMod(self.width, self.id_wid)
-        chain = StageChain([nmod, rmod, cmod, pmod])
+        stages = [nmod, rmod, cmod, pmod]
+        chain = StageChain(stages)
         chain.setup(m, i)
         self.out_z = pmod.ospec()
 

diff --git a/src/add/fpcommon/pack.py b/src/add/fpcommon/pack.py
index 97d6911105f2121d0bcadefc47cdbe90a956f38f..1464883cdeec57ed4fcc002ecb192b557f7db4fc 100644 (file)
--- a/src/add/fpcommon/pack.py
+++ b/src/add/fpcommon/pack.py
@@ -2,7 +2,7 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal
+from nmigen import Module, Signal, Elaboratable
 from nmigen.cli import main, verilog
 
 from fpbase import FPNumOut
@@ -19,7 +19,7 @@ class FPPackData(Object):
         self.mid = Signal(id_wid, reset_less=True)
 
 
-class FPPackMod:
+class FPPackMod(Elaboratable):
 
     def __init__(self, width, id_wid):
         self.width = width

diff --git a/src/add/fpcommon/postnormalise.py b/src/add/fpcommon/postnormalise.py
index c60adbca1b5602f6573f961af18d3db91ac7c762..b072490f0374fab9872c9c846fa9efa161480c07 100644 (file)
--- a/src/add/fpcommon/postnormalise.py
+++ b/src/add/fpcommon/postnormalise.py
@@ -2,7 +2,7 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Cat, Mux
+from nmigen import Module, Signal, Cat, Mux, Elaboratable
 from nmigen.lib.coding import PriorityEncoder
 from nmigen.cli import main, verilog
 from math import log
@@ -27,7 +27,7 @@ class FPNorm1Data:
                 self.roundz.eq(i.roundz), self.mid.eq(i.mid)]
 
 
-class FPNorm1ModSingle:
+class FPNorm1ModSingle(Elaboratable):
 
     def __init__(self, width, id_wid):
         self.width = width

diff --git a/src/add/fpcommon/roundz.py b/src/add/fpcommon/roundz.py
index 24c49b87d9c67059bd634932cf61306310a0eab4..420d6669a10799190f23585b1d09c31dad118af2 100644 (file)
--- a/src/add/fpcommon/roundz.py
+++ b/src/add/fpcommon/roundz.py
@@ -2,7 +2,7 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal
+from nmigen import Module, Signal, Elaboratable
 from nmigen.cli import main, verilog
 
 from fpbase import FPNumBase
@@ -23,7 +23,7 @@ class FPRoundData:
                 self.mid.eq(i.mid)]
 
 
-class FPRoundMod:
+class FPRoundMod(Elaboratable):
 
     def __init__(self, width, id_wid):
         self.width = width