projects
/
nmigen.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
4415def
)
wip (#439)
24jan2021_ls180
author
whitequark
<whitequark@whitequark.org>
Wed, 22 Jul 2020 12:14:39 +0000
(12:14 +0000)
committer
whitequark
<whitequark@whitequark.org>
Wed, 22 Jul 2020 14:56:38 +0000
(14:56 +0000)
nmigen/sim/cxxsim.py
patch
|
blob
|
history
diff --git
a/nmigen/sim/cxxsim.py
b/nmigen/sim/cxxsim.py
index a637c85ca8d09ace334fc26a7c53d3fbea03f32f..5edce5da7b827831b051f44597ee432ddf3d60ae 100644
(file)
--- a/
nmigen/sim/cxxsim.py
+++ b/
nmigen/sim/cxxsim.py
@@
-116,13
+116,13
@@
class Simulator(SimulatorCore):
process.reset()
def _real_step(self):
- for process in self._processes:
- if process.runnable:
- process.runnable = False
- process.run()
-
while True:
self._state.eval()
+ for process in self._processes:
+ if process.runnable:
+ process.runnable = False
+ process.run()
+
if not self._state.commit():
break