From: Alex Solomatnikov <sols@sifive.com>
Date: Thu, 9 Feb 2017 19:37:40 +0000 (-0800)
Subject: Flipped polarity of output enables to match Guava pins logic
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=095cb158dd0e7fe87b3cf5afa30b6db3ec4dc266;hp=72e4b60d81e5ae1cbc518c9a3bda486a56dfca8c;p=sifive-blocks.git

Flipped polarity of output enables to match Guava pins logic
---

diff --git a/src/main/scala/devices/i2c/I2C.scala b/src/main/scala/devices/i2c/I2C.scala
index da55549..0c48764 100644
--- a/src/main/scala/devices/i2c/I2C.scala
+++ b/src/main/scala/devices/i2c/I2C.scala
@@ -182,10 +182,10 @@ trait I2CModule extends Module with HasI2CParameters with HasRegMap {
   }
 
   val sclOen     = Reg(init = true.B)
-  io.port.scl.oe := sclOen
+  io.port.scl.oe := !sclOen
 
   val sdaOen     = Reg(init = true.B)
-  io.port.sda.oe := sdaOen
+  io.port.sda.oe := !sdaOen
 
   val sdaChk     = Reg(init = false.B)       // check SDA output (Multi-master arbitration)