From: Luke Kenneth Casson Leighton Date: Tue, 5 Dec 2023 14:46:56 +0000 (+0000) Subject: remove redundant symbols X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=150f8ee5805c2a25f18cc2cdcfea9b479c139e93;p=libreriscv.git remove redundant symbols --- diff --git a/openpower/sv/cookbook/pospopcnt.mdwn b/openpower/sv/cookbook/pospopcnt.mdwn index 9a2d619f6..9e0046463 100644 --- a/openpower/sv/cookbook/pospopcnt.mdwn +++ b/openpower/sv/cookbook/pospopcnt.mdwn @@ -26,9 +26,9 @@ A simple but still hardware-paralleliseable SVP64 assembler for 8-bit input values (`count8safe`) is as follows: ``` -mtspr 9, 3" # move r3 to CTR +mtspr 9, 3 # move r3 to CTR # VL = MIN(CTR,MAXVL=8), Rc=1 (CR0 set if CTR ends) -setvl 3,0,8,0,1,1" # set MVL=8, VL=MIN(MVL,CTR) +setvl 3,0,8,0,1,1 # set MVL=8, VL=MIN(MVL,CTR) # load VL bytes (update r4 addr) but compressed (dw=8) addi 6, 0, 0 # initialise all 64-bits of r6 to zero sv.lbzu/pi/dw=8 *6, 1(4) # should be /lf here as well @@ -61,7 +61,7 @@ Firstly the CTR (Counter) SPR is set up, and is key to looping as outlined further, below ``` -mtspr 9, 3" # move r3 to CTR +mtspr 9, 3 # move r3 to CTR ``` The Vector Length, which is limited to 8 (MVL - Maximum @@ -81,7 +81,7 @@ a copy of VL into a GPR. ``` # VL = MIN(CTR,MAXVL=8) -setvl 3,0,8,0,1,1" # set MVL=8, VL=MIN(MVL,CTR) +setvl 3,0,8,0,1,1 # set MVL=8, VL=MIN(MVL,CTR) ``` ```