From: Cesar Strauss <cestrauss@gmail.com>
Date: Sat, 17 Apr 2021 18:12:29 +0000 (-0300)
Subject: Implement 1<<r3 directly by a shift
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1e3cd18cc5fa1551b047aaa7f0ca008b76b8fb2d;p=soc.git

Implement 1<<r3 directly by a shift

It generates simpler Yosys graphs.
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index b2711cbb..9df03bb0 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -471,7 +471,7 @@ class TestIssuerInternal(Elaboratable):
                     # set selected mask bit for 1<<r3 mode
                     dst_shift = Signal(range(64))
                     comb += dst_shift.eq(self.int_pred.data_o & 0b111111)
-                    comb += new_dstmask.bit_select(dst_shift, 1).eq(1)
+                    comb += new_dstmask.eq(1 << dst_shift)
                 with m.Else():
                     # invert mask if requested
                     comb += new_dstmask.eq(self.int_pred.data_o ^ inv)
@@ -495,7 +495,7 @@ class TestIssuerInternal(Elaboratable):
                     # set selected mask bit for 1<<r3 mode
                     src_shift = Signal(range(64))
                     comb += src_shift.eq(self.int_pred.data_o & 0b111111)
-                    comb += new_srcmask.bit_select(src_shift, 1).eq(1)
+                    comb += new_srcmask.eq(1 << src_shift)
                 with m.Else():
                     # invert mask if requested
                     comb += new_srcmask.eq(self.int_pred.data_o ^ inv)