From: Andrew Waterman Date: Tue, 17 Mar 2015 08:18:36 +0000 (-0700) Subject: Merge [shm]call into ecall, [shm]ret into eret X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=211d78276b07b17f831cefaf79961d3e6dad3c90;p=riscv-tests.git Merge [shm]call into ecall, [shm]ret into eret --- diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S index debee6d..19ff3b2 100644 --- a/benchmarks/common/crt.S +++ b/benchmarks/common/crt.S @@ -135,7 +135,7 @@ _start: la t0, _init csrw mepc, t0 - mret + eret trap_entry: addi sp, sp, -272 @@ -211,7 +211,7 @@ trap_entry: LREG x31, 248(sp) addi sp, sp, 272 - mret + eret .section ".tdata.begin" .globl _tdata_begin diff --git a/benchmarks/common/syscalls.c b/benchmarks/common/syscalls.c index 12dab70..b1c100d 100644 --- a/benchmarks/common/syscalls.c +++ b/benchmarks/common/syscalls.c @@ -75,7 +75,7 @@ long handle_trap(long cause, long epc, long regs[32]) if (cause == CAUSE_ILLEGAL_INSTRUCTION && (*(int*)epc & *csr_insn) == *csr_insn) ; - else if (cause != CAUSE_SCALL) + else if (cause != CAUSE_ECALL) tohost_exit(1337); else if (regs[17] == SYS_exit) tohost_exit(regs[10]); diff --git a/env b/env index be65116..9d64d05 160000 --- a/env +++ b/env @@ -1 +1 @@ -Subproject commit be6511639c2d9291e9050682c4d7ce3e7042d061 +Subproject commit 9d64d0579feaac16578158b29c94767823f19a83 diff --git a/isa/rv32si/scall.S b/isa/rv32si/scall.S index c5cc3ac..a036aaf 100644 --- a/isa/rv32si/scall.S +++ b/isa/rv32si/scall.S @@ -25,7 +25,7 @@ RVTEST_CODE_BEGIN TEST_PASSFAIL stvec: - li t1, CAUSE_SCALL + li t1, CAUSE_ECALL csrr t0, scause bne t0, t1, fail csrr t0, sepc diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S index 2a326a6..edaaeb3 100644 --- a/isa/rv64si/csr.S +++ b/isa/rv64si/csr.S @@ -78,7 +78,7 @@ privileged: syscall: # Make sure CAUSE indicates a syscall. csrr t0, scause - li t1, CAUSE_SCALL + li t1, CAUSE_ECALL bne t0, t1, fail # We're done. diff --git a/isa/rv64si/dirty.S b/isa/rv64si/dirty.S index 87a619a..78e333b 100644 --- a/isa/rv64si/dirty.S +++ b/isa/rv64si/dirty.S @@ -23,7 +23,7 @@ RVTEST_CODE_BEGIN csrs mstatus, a1 la a1, 1f csrw mepc, a1 - mret + eret 1: # Try a faulting store to make sure dirty bit is not set