From: Megan Wachs <megan@sifive.com>
Date: Fri, 10 Mar 2017 22:09:24 +0000 (-0800)
Subject: Merge remote-tracking branch 'origin/master' into debug-0.13
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=25356957fec64ecbae15b7fa85e1d3e536bbce1b;hp=062203ae18fc7a25114fb5746f636a0439cc6cec;p=sifive-blocks.git

Merge remote-tracking branch 'origin/master' into debug-0.13
---

diff --git a/src/main/scala/devices/gpio/JTAG.scala b/src/main/scala/devices/gpio/JTAG.scala
index 8734539..d16cf32 100644
--- a/src/main/scala/devices/gpio/JTAG.scala
+++ b/src/main/scala/devices/gpio/JTAG.scala
@@ -11,7 +11,7 @@ import Chisel._
 // ------------------------------------------------------------
 
 import config._
-import junctions.{JTAGIO}
+import jtag.{JTAGIO}
 
 class JTAGPinsIO extends Bundle {
 
@@ -19,25 +19,22 @@ class JTAGPinsIO extends Bundle {
   val TMS    = new GPIOPin()
   val TDI    = new GPIOPin()
   val TDO    = new GPIOPin()
-  val TRST_n = new GPIOPin()
+  val TRSTn = new GPIOPin()
 
 }
 
-class JTAGGPIOPort(drvTdo: Boolean = false)(implicit p: Parameters) extends Module {
+class JTAGGPIOPort()(implicit p: Parameters) extends Module {
 
   val io = new Bundle {
-    val jtag = new JTAGIO(drvTdo)
+    val jtag = new JTAGIO()
     val pins = new JTAGPinsIO()
   }
 
   io.jtag.TCK  := GPIOInputPinCtrl(io.pins.TCK, pue = Bool(true)).asClock
   io.jtag.TMS  := GPIOInputPinCtrl(io.pins.TMS, pue = Bool(true))
   io.jtag.TDI  := GPIOInputPinCtrl(io.pins.TDI, pue = Bool(true))
-  io.jtag.TRST := ~GPIOInputPinCtrl(io.pins.TRST_n, pue = Bool(true))
-
-  GPIOOutputPinCtrl(io.pins.TDO, io.jtag.TDO)
-  if (drvTdo) {
-    io.pins.TDO.o.oe := io.jtag.DRV_TDO.get
-  }
+  io.jtag.TRSTn := GPIOInputPinCtrl(io.pins.TRSTn, pue = Bool(true))
 
+  GPIOOutputPinCtrl(io.pins.TDO, io.jtag.TDO.data)
+  io.pins.TDO.o.oe := io.jtag.TDO.driven
 }