From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 21 Dec 2023 16:33:34 +0000 (+0000)
Subject: bug 676: although spotted under maxloc, sv.mcrf was incomplete
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2711268327d2d15ad4d268e3f0982beba5232a64;p=openpower-isa.git

bug 676: although spotted under maxloc, sv.mcrf was incomplete

https://bugs.libre-soc.org/show_bug.cgi?id=1239
BF was "vectorised" (through a rewrite of the immediate field)
but BFA was not. a *lot* more unit tests are needed for ISACaller
to be "up to spec"
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 7ed040e2..c6f255ba 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -427,13 +427,15 @@ def _get_predcr(mask):
 
 # read individual CR fields (0..VL-1), extract the required bit
 # and construct the mask
-def get_predcr(crl, mask, vl):
-    idx, noninv = _get_predcr(mask)
+def get_predcr(crl, predselect, vl):
+    idx, noninv = _get_predcr(predselect)
     mask = 0
     for i in range(vl):
         cr = crl[i+SVP64CROffs.CRPred]
         if cr[idx].value == noninv:
             mask |= (1 << i)
+        log("get_predcr", vl, idx, noninv, i+SVP64CROffs.CRPred,
+                          bin(cr.asint()), cr[idx].value, bin(mask))
     return mask
 
 
@@ -560,6 +562,9 @@ def get_cr_in(dec2, name):
     if name == 'BI':
         if in_sel == CRInSel.BI.value:
             return in1, cr_isvec
+    if name == 'BFA':
+        if in_sel == CRInSel.BFA.value:
+            return in1, cr_isvec
     log("get_cr_in not found", name)
     return None, False
 
@@ -1642,6 +1647,10 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
                 # low 2 LSBs (CR field selector) remain same, CR num extended
                 assert regnum <= 7, "sigh, TODO, 128 CR fields"
                 val = (val & 0b11) | (regnum << 2)
+            elif self.is_svp64_mode and name in ['BFA']:  # TODO, more CRs
+                regnum, is_vec = yield from get_cr_in(self.dec2, name)
+                log('hack %s' % name, regnum, is_vec)
+                val = regnum
             elif self.is_svp64_mode and name in ['BF']:  # TODO, more CRs
                 regnum, is_vec = yield from get_cr_out(self.dec2, "BF")
                 log('hack %s' % name, regnum, is_vec)