From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 17 Apr 2021 08:03:09 +0000 (+0100)
Subject: comment on why clocks are in FSM
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2a96c30b86cef7cf83f64c51a216182de7eabe04;p=c4m-jtag.git

comment on why clocks are in FSM
---

diff --git a/c4m/nmigen/jtag/tap.py b/c4m/nmigen/jtag/tap.py
index a997554..525b531 100755
--- a/c4m/nmigen/jtag/tap.py
+++ b/c4m/nmigen/jtag/tap.py
@@ -25,6 +25,7 @@ class _FSM(Elaboratable):
         self.shift = Signal()
         self.update = Signal()
 
+        # JTAG uses both edges of the incoming clock (TCK). set them up here
         self.posjtag = ClockDomain("posjtag", local=True)
         self.negjtag = ClockDomain("negjtag", local=True, clk_edge="neg")