From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 14 May 2019 09:02:54 +0000 (+0100)
Subject: inverted global write pend vector, on creation of readable signal,
X-Git-Tag: div_pipeline~2047
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2b576334da7ce62d364b17442c8de1a777b5c282;p=soc.git

inverted global write pend vector, on creation of readable signal,
seems to work
---

diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py
index 3d73b3b3..0d1fc4d5 100644
--- a/src/experiment/cscore.py
+++ b/src/experiment/cscore.py
@@ -305,7 +305,7 @@ def scoreboard_sim(dut, alusim):
 
         yield from alusim.check(dut)
 
-    for i in range(1):
+    for i in range(20):
         src1 = randint(1, dut.n_regs-1)
         src2 = randint(1, dut.n_regs-1)
         while True:
@@ -313,12 +313,12 @@ def scoreboard_sim(dut, alusim):
             break
             if dest not in [src1, src2]:
                 break
-        src1 = 2
-        src2 = 2
-        dest = 2
+        #src1 = 2
+        #src2 = 3
+        #dest = 2 
 
         op = randint(0, 1)
-        op = 0
+        #op = 1
         print ("random %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
         yield from int_instr(dut, alusim, op, src1, src2, dest)
         yield from print_reg(dut, [3,4,5])
@@ -328,7 +328,6 @@ def scoreboard_sim(dut, alusim):
             yield dut.int_insn_i[i].eq(0)
         yield
         yield
-        yield
 
 
     yield
diff --git a/src/scoreboard/fn_unit.py b/src/scoreboard/fn_unit.py
index 26a15194..1e597cda 100644
--- a/src/scoreboard/fn_unit.py
+++ b/src/scoreboard/fn_unit.py
@@ -161,7 +161,7 @@ class FnUnit(Elaboratable):
 
         # readable output signal
         g_rd = Signal(self.reg_width, reset_less=True)
-        m.d.comb += g_rd.eq(self.g_wr_pend_i & self.rd_pend_o)
+        m.d.comb += g_rd.eq((~self.g_wr_pend_i) & self.rd_pend_o)
         m.d.comb += self.readable_o.eq(g_rd.bool())
 
         # writable output signal