From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 29 Jan 2024 14:04:59 +0000 (+0000)
Subject: shorten call to ISACaller.prep_namespace
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3327cb7f7eea1a939940667eac64b4ce3c58e217;p=openpower-isa.git

shorten call to ISACaller.prep_namespace
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 2544c61a..9f362676 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1623,12 +1623,13 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
     def memassign(self, ea, sz, val):
         self.mem.memassign(ea, sz, val)
 
-    def prep_namespace(self, insn_name, formname, op_fields, xlen):
+    def prep_namespace(self, insn_name, info, xlen):
         # TODO: get field names from form in decoder*1* (not decoder2)
         # decoder2 is hand-created, and decoder1.sigform is auto-generated
         # from spec
         # then "yield" fields only from op_fields rather than hard-coded
         # list, here.
+        formname, op_fields = info.form, info.op_fields
         fields = self.decoder.sigforms[formname]
         log("prep_namespace", formname, op_fields, insn_name)
         for name in op_fields:
@@ -2353,8 +2354,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
             info = self.instrs[asmop]
         else:
             info = self.instrs[ins_name]
-        yield from self.prep_namespace(ins_name, info.form, info.op_fields,
-                                       xlen)
+        yield from self.prep_namespace(ins_name, info, xlen)
 
         # dict retains order
         inputs = dict.fromkeys(create_full_args(