From: Luke Kenneth Casson Leighton Date: Sun, 19 May 2019 09:34:02 +0000 (+0100) Subject: use register-based DepCell X-Git-Tag: div_pipeline~2013 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=35657072e23e1db99d523566029c16fdc9dbd083;p=soc.git use register-based DepCell --- diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py index b4df27e5..d03a8d2c 100644 --- a/src/experiment/compalu.py +++ b/src/experiment/compalu.py @@ -54,7 +54,7 @@ class ComputationUnitNoDelay(Elaboratable): m.d.comb += self.busy_o.eq(opc_l.q) # busy out with m.If(req_l.qn & opc_l.q & (self.counter == 0)): - m.d.sync += self.counter.eq(5) + m.d.sync += self.counter.eq(3) with m.If(self.counter > 0): m.d.sync += self.counter.eq(self.counter - 1) with m.If((self.counter == 1) | (self.counter == 0)): diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py index 6637d280..078c2b5b 100644 --- a/src/experiment/score6600.py +++ b/src/experiment/score6600.py @@ -253,8 +253,8 @@ class Scoreboard(Elaboratable): # Connect Picker #--------- - #m.d.comb += intpick1.go_rd_i[0:2].eq(~go_rd_i[0:2]) - m.d.comb += intpick1.go_rd_i[0:2].eq(cu.req_rel_o[0:2]) + m.d.comb += intpick1.rd_rel_i[0:2].eq(~go_rd_i[0:2] & cu.busy_o[0:2]) + #m.d.comb += intpick1.go_rd_i[0:2].eq(cu.req_rel_o[0:2]) m.d.comb += intpick1.req_rel_i[0:2].eq(cu.req_rel_o[0:2]) int_readable_o = intfus.readable_o int_writable_o = intfus.writable_o @@ -388,7 +388,7 @@ def scoreboard_sim(dut, alusim): if True: instrs.append((1, 1, 2, 0)) - instrs.append((3, 7, 1, 1)) + #instrs.append((2, 7, 1, 1)) #instrs.append((2, 2, 3, 1)) for i, (src1, src2, dest, op) in enumerate(instrs): @@ -408,6 +408,10 @@ def scoreboard_sim(dut, alusim): yield from print_reg(dut, [3,4,5]) yield + yield + yield from print_reg(dut, [3,4,5]) + yield + yield from print_reg(dut, [3,4,5]) yield yield from print_reg(dut, [3,4,5]) yield diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py index e448588a..d0dbbefc 100644 --- a/src/scoreboard/dependence_cell.py +++ b/src/scoreboard/dependence_cell.py @@ -36,7 +36,7 @@ class DepCell(Elaboratable): m.d.comb += self.fwd_o.eq((cq | l.q) & self.reg_i) # Register Select. Activated on go read/write and *current* latch set - m.d.comb += self.rsel_o.eq(cq & self.go_i) + m.d.comb += self.rsel_o.eq((cq | l.q) & self.go_i) return m @@ -76,31 +76,31 @@ class DependenceCell(Elaboratable): def elaborate(self, platform): m = Module() - m.submodules.dest_l = dest_l = SRLatch(sync=False) # clock-sync'd - m.submodules.src1_l = src1_l = SRLatch(sync=False) # clock-sync'd - m.submodules.src2_l = src2_l = SRLatch(sync=False) # clock-sync'd - - # destination latch: reset on go_wr HI, set on dest and issue - m.d.comb += dest_l.s.eq(self.issue_i & self.dest_i) - m.d.comb += dest_l.r.eq(self.go_wr_i) - - # src1 latch: reset on go_rd HI, set on src1_i and issue - m.d.comb += src1_l.s.eq(self.issue_i & self.src1_i) - m.d.comb += src1_l.r.eq(self.go_rd_i) - - # src2 latch: reset on go_rd HI, set on op2_i and issue - m.d.comb += src2_l.s.eq(self.issue_i & self.src2_i) - m.d.comb += src2_l.r.eq(self.go_rd_i) - - # FU "Forward Progress" (read out vertically) - m.d.comb += self.dest_fwd_o.eq(dest_l.q & self.dest_i) - m.d.comb += self.src1_fwd_o.eq(src1_l.q & self.src1_i) - m.d.comb += self.src2_fwd_o.eq(src2_l.q & self.src2_i) - - # Register File Select (read out horizontally) - m.d.sync += self.dest_rsel_o.eq(dest_l.q & ~self.go_wr_i) - m.d.sync += self.src1_rsel_o.eq(src1_l.q & ~self.go_rd_i) - m.d.sync += self.src2_rsel_o.eq(src2_l.q & ~self.go_rd_i) + m.submodules.dest_c = dest_c = DepCell() + m.submodules.src1_c = src1_c = DepCell() + m.submodules.src2_c = src2_c = DepCell() + + # connect issue + for c in [dest_c, src1_c, src2_c]: + m.d.comb += c.issue_i.eq(self.issue_i) + + # connect go_rd / go_wr (dest->wr, src->rd) + m.d.comb += dest_c.go_i.eq(self.go_wr_i) + m.d.comb += src1_c.go_i.eq(self.go_rd_i) + m.d.comb += src2_c.go_i.eq(self.go_rd_i) + + # connect input reg bit (unary) + for c, reg in [(dest_c, self.dest_i), + (src1_c, self.src1_i), + (src2_c, self.src2_i)]: + m.d.comb += c.reg_i.eq(reg) + + # connect fwd / reg-sel outputs + for c, fwd, rsel in [(dest_c, self.dest_fwd_o, self.dest_rsel_o), + (src1_c, self.src1_fwd_o, self.src1_rsel_o), + (src2_c, self.src2_fwd_o, self.src2_rsel_o)]: + m.d.comb += fwd.eq(c.fwd_o) + m.d.comb += rsel.eq(c.rsel_o) return m diff --git a/src/scoreboard/group_picker.py b/src/scoreboard/group_picker.py index e5fad249..f02f8863 100644 --- a/src/scoreboard/group_picker.py +++ b/src/scoreboard/group_picker.py @@ -34,7 +34,7 @@ class PriorityPicker(Elaboratable): def __iter__(self): yield self.i yield self.o - + def ports(self): return list(self) @@ -47,7 +47,7 @@ class GroupPicker(Elaboratable): # inputs self.readable_i = Signal(wid, reset_less=True) # readable in (top) self.writable_i = Signal(wid, reset_less=True) # writable in (top) - self.go_rd_i = Signal(wid, reset_less=True) # go read in (top) + self.rd_rel_i = Signal(wid, reset_less=True) # go read in (top) self.req_rel_i = Signal(wid, reset_less=True) # release request in (top) # outputs @@ -64,7 +64,7 @@ class GroupPicker(Elaboratable): m.d.comb += wpick.i.eq(self.writable_i & self.req_rel_i) m.d.comb += self.go_wr_o.eq(wpick.o) - m.d.comb += rpick.i.eq(self.readable_i) #& self.go_rd_i) + m.d.comb += rpick.i.eq(self.readable_i & self.rd_rel_i) m.d.comb += self.go_rd_o.eq(rpick.o) return m @@ -93,9 +93,9 @@ def grp_pick_sim(dut): yield yield dut.issue_i.eq(0) yield - yield dut.go_rd_i.eq(1) + yield dut.rd_rel_i.eq(1) yield - yield dut.go_rd_i.eq(0) + yield dut.rd_rel_i.eq(0) yield yield dut.go_wr_i.eq(1) yield