From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 28 Feb 2019 13:15:53 +0000 (+0000)
Subject: use output from align as input to add0
X-Git-Tag: ls180-24jan2020~1791
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3d0b7f7818a35c8284e45b9a32c2428e3adba7d0;p=ieee754fpu.git

use output from align as input to add0
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 0bc19a33..1b9fca1f 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -811,9 +811,9 @@ class FPADD:
         m.submodules.align = alm.mod
 
         add0 = self.add_state(FPAddStage0(self.width))
-        add0.set_inputs({"a": a, "b": b})
+        add0.set_inputs({"a": alm.out_a, "b": alm.out_b})
         add0.set_outputs({"z": z})
-        add0.mod.setup(m, a, b, z, add0.out_z, add0.out_tot)
+        add0.mod.setup(m, alm.out_a, alm.out_b, z, add0.out_z, add0.out_tot)
         m.submodules.add0 = add0.mod
 
         add1 = self.add_state(FPAddStage1(self.width))