From: Andrew Waterman Date: Thu, 3 Mar 2016 06:33:37 +0000 (-0800) Subject: Some S-mode tests really only belong in M-mode X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4d1491df727e9aeb5fdfeac25c22eaf24cafb908;p=riscv-tests.git Some S-mode tests really only belong in M-mode --- diff --git a/isa/rv32mi/Makefrag b/isa/rv32mi/Makefrag index 7560dbc..3a5b376 100644 --- a/isa/rv32mi/Makefrag +++ b/isa/rv32mi/Makefrag @@ -9,6 +9,7 @@ rv32mi_sc_tests = \ ma_addr \ scall \ sbreak \ + shamt \ timer \ rv32mi_mc_tests = \ diff --git a/isa/rv32mi/illegal.S b/isa/rv32mi/illegal.S index c357ed7..e167c71 100644 --- a/isa/rv32mi/illegal.S +++ b/isa/rv32mi/illegal.S @@ -1,8 +1,7 @@ # See LICENSE for license details. #include "riscv_test.h" -#undef RVTEST_RV64S -#define RVTEST_RV64S RVTEST_RV32M -#define __MACHINE_MODE +#undef RVTEST_RV64M +#define RVTEST_RV64M RVTEST_RV32M -#include "../rv64si/illegal.S" +#include "../rv64mi/illegal.S" diff --git a/isa/rv32mi/ma_addr.S b/isa/rv32mi/ma_addr.S index df5099a..7575a3f 100644 --- a/isa/rv32mi/ma_addr.S +++ b/isa/rv32mi/ma_addr.S @@ -1,8 +1,7 @@ # See LICENSE for license details. #include "riscv_test.h" -#undef RVTEST_RV64S -#define RVTEST_RV64S RVTEST_RV32M -#define __MACHINE_MODE +#undef RVTEST_RV64M +#define RVTEST_RV64M RVTEST_RV32M -#include "../rv64si/ma_addr.S" +#include "../rv64mi/ma_addr.S" diff --git a/isa/rv32mi/shamt.S b/isa/rv32mi/shamt.S new file mode 100644 index 0000000..2c92412 --- /dev/null +++ b/isa/rv32mi/shamt.S @@ -0,0 +1,43 @@ +# See LICENSE for license details. + +#***************************************************************************** +# csr.S +#----------------------------------------------------------------------------- +# +# Test CSRRx and CSRRxI instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32M +RVTEST_CODE_BEGIN + + # Make sure slli with shamt[4] set is legal. + TEST_CASE( 2, a0, 65536, li a0, 1; slli a0, a0, 16); + + # Make sure slli with shamt[5] set is not legal. + TEST_CASE( 3, x0, 1, slli a0, a0, 32); + + TEST_PASSFAIL + +mtvec_handler: + # Trapping on test 3 is good. + # Note that since the test didn't complete, TESTNUM is smaller by 1. + li t0, 2 + bne TESTNUM, t0, fail + + # Make sure CAUSE indicates an illegal instructino. + csrr t0, mcause + li t1, CAUSE_ILLEGAL_INSTRUCTION + bne t0, t1, fail + j pass + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32si/Makefrag b/isa/rv32si/Makefrag index 1283ec4..dea3ecf 100644 --- a/isa/rv32si/Makefrag +++ b/isa/rv32si/Makefrag @@ -4,12 +4,9 @@ rv32si_sc_tests = \ csr \ - shamt \ ma_fetch \ - illegal \ scall \ sbreak \ - ma_addr \ rv32si_p_tests = $(addprefix rv32si-p-, $(rv32si_sc_tests)) diff --git a/isa/rv32si/illegal.S b/isa/rv32si/illegal.S deleted file mode 100644 index ad5c3b1..0000000 --- a/isa/rv32si/illegal.S +++ /dev/null @@ -1,7 +0,0 @@ -# See LICENSE for license details. - -#include "riscv_test.h" -#undef RVTEST_RV64S -#define RVTEST_RV64S RVTEST_RV32S - -#include "../rv64si/illegal.S" diff --git a/isa/rv32si/ma_addr.S b/isa/rv32si/ma_addr.S deleted file mode 100644 index 51465a2..0000000 --- a/isa/rv32si/ma_addr.S +++ /dev/null @@ -1,7 +0,0 @@ -# See LICENSE for license details. - -#include "riscv_test.h" -#undef RVTEST_RV64S -#define RVTEST_RV64S RVTEST_RV32S - -#include "../rv64si/ma_addr.S" diff --git a/isa/rv32si/shamt.S b/isa/rv32si/shamt.S deleted file mode 100644 index 615ef68..0000000 --- a/isa/rv32si/shamt.S +++ /dev/null @@ -1,46 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# csr.S -#----------------------------------------------------------------------------- -# -# Test CSRRx and CSRRxI instructions. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32S -RVTEST_CODE_BEGIN - - la t0, stvec_handler - csrw stvec, t0 - - # Make sure slli with shamt[4] set is legal. - TEST_CASE( 2, a0, 65536, li a0, 1; slli a0, a0, 16); - - # Make sure slli with shamt[5] set is not legal. - TEST_CASE( 3, x0, 1, slli a0, a0, 32); - - TEST_PASSFAIL - -stvec_handler: - # Trapping on test 3 is good. - # Note that since the test didn't complete, TESTNUM is smaller by 1. - li t0, 2 - bne TESTNUM, t0, fail - - # Make sure CAUSE indicates an illegal instructino. - csrr t0, scause - li t1, CAUSE_ILLEGAL_INSTRUCTION - bne t0, t1, fail - j pass - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64mi/illegal.S b/isa/rv64mi/illegal.S index c5ccffd..ecb3088 100644 --- a/isa/rv64mi/illegal.S +++ b/isa/rv64mi/illegal.S @@ -1,8 +1,40 @@ # See LICENSE for license details. +#***************************************************************************** +# illegal.S +#----------------------------------------------------------------------------- +# +# Test illegal instruction trap. +# + #include "riscv_test.h" -#undef RVTEST_RV64S -#define RVTEST_RV64S RVTEST_RV64M -#define __MACHINE_MODE +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + li TESTNUM, 2 + .word 0 + j fail + + j pass + + TEST_PASSFAIL + +mtvec_handler: + li t1, CAUSE_ILLEGAL_INSTRUCTION + csrr t0, mcause + bne t0, t1, fail + csrr t0, mepc + addi t0, t0, 8 + csrw mepc, t0 + sret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA -#include "../rv64si/illegal.S" +RVTEST_DATA_END diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S index 0448736..aa5dd85 100644 --- a/isa/rv64mi/ma_addr.S +++ b/isa/rv64mi/ma_addr.S @@ -1,8 +1,84 @@ # See LICENSE for license details. +#***************************************************************************** +# ma_addr.S +#----------------------------------------------------------------------------- +# +# Test misaligned ld/st trap. +# + #include "riscv_test.h" -#undef RVTEST_RV64S -#define RVTEST_RV64S RVTEST_RV64M -#define __MACHINE_MODE +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + .align 3 + auipc s0, 0 + + # indicate it's a load test + li s1, CAUSE_MISALIGNED_LOAD + +#define MISALIGNED_LDST_TEST(testnum, insn, base, offset) \ + li TESTNUM, testnum; \ + insn x0, offset(base); \ + j fail \ + + MISALIGNED_LDST_TEST(2, lh, s0, 1) + MISALIGNED_LDST_TEST(3, lhu, s0, 1) + MISALIGNED_LDST_TEST(4, lw, s0, 1) + MISALIGNED_LDST_TEST(5, lw, s0, 2) + MISALIGNED_LDST_TEST(6, lw, s0, 3) + +#ifdef __riscv64 + MISALIGNED_LDST_TEST(7, lwu, s0, 1) + MISALIGNED_LDST_TEST(8, lwu, s0, 2) + MISALIGNED_LDST_TEST(9, lwu, s0, 3) + + MISALIGNED_LDST_TEST(10, ld, s0, 1) + MISALIGNED_LDST_TEST(11, ld, s0, 2) + MISALIGNED_LDST_TEST(12, ld, s0, 3) + MISALIGNED_LDST_TEST(13, ld, s0, 4) + MISALIGNED_LDST_TEST(14, ld, s0, 5) + MISALIGNED_LDST_TEST(15, ld, s0, 6) + MISALIGNED_LDST_TEST(16, ld, s0, 7) +#endif + + # indicate it's a store test + li s1, CAUSE_MISALIGNED_STORE + + MISALIGNED_LDST_TEST(22, sh, s0, 1) + MISALIGNED_LDST_TEST(23, sw, s0, 1) + MISALIGNED_LDST_TEST(24, sw, s0, 2) + MISALIGNED_LDST_TEST(25, sw, s0, 3) + +#ifdef __riscv64 + MISALIGNED_LDST_TEST(26, sd, s0, 1) + MISALIGNED_LDST_TEST(27, sd, s0, 2) + MISALIGNED_LDST_TEST(28, sd, s0, 3) + MISALIGNED_LDST_TEST(29, sd, s0, 4) + MISALIGNED_LDST_TEST(30, sd, s0, 5) + MISALIGNED_LDST_TEST(31, sd, s0, 6) + MISALIGNED_LDST_TEST(32, sd, s0, 7) +#endif + + TEST_PASSFAIL + + .align 3 +mtvec_handler: + csrr t0, mcause + bne t0, s1, fail + + csrr t0, mepc + addi t0, t0, 8 + csrw mepc, t0 + sret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA -#include "../rv64si/ma_addr.S" +RVTEST_DATA_END diff --git a/isa/rv64si/Makefrag b/isa/rv64si/Makefrag index 9c5db64..076ea59 100644 --- a/isa/rv64si/Makefrag +++ b/isa/rv64si/Makefrag @@ -4,9 +4,7 @@ rv64si_sc_tests = \ csr \ - illegal \ ma_fetch \ - ma_addr \ scall \ wfi \ sbreak \ diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S index af0b756..d0c6724 100644 --- a/isa/rv64si/csr.S +++ b/isa/rv64si/csr.S @@ -34,7 +34,10 @@ RVTEST_CODE_BEGIN TEST_CASE( 9, a0, 0xbadbeef, csrr a0, sscratch); # Make sure writing the cycle counter causes an exception. + # Don't run in supervisor, as we don't delegate illegal instruction traps. +#ifdef __MACHINE_MODE TEST_CASE(10, a0, 255, li a0, 255; csrrw a0, cycle, x0); +#endif # jump to user land li t0, SSTATUS_SPP @@ -45,7 +48,12 @@ RVTEST_CODE_BEGIN 1: # Make sure reading status in user mode causes an exception. - TEST_CASE(11, a0, 255, li a0, 255; csrr a0, sstatus); + # Don't run in supervisor, as we don't delegate illegal instruction traps. +#ifdef __MACHINE_MODE + TEST_CASE(11, a0, 255, li a0, 255; csrr a0, sstatus) +#else + TEST_CASE(11, x0, 0, nop) +#endif # Exit by doing a syscall. TEST_CASE(12, x0, 1, scall) diff --git a/isa/rv64si/illegal.S b/isa/rv64si/illegal.S deleted file mode 100644 index 43068b4..0000000 --- a/isa/rv64si/illegal.S +++ /dev/null @@ -1,48 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# illegal.S -#----------------------------------------------------------------------------- -# -# Test illegal instruction trap. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64S -RVTEST_CODE_BEGIN - -#ifdef __MACHINE_MODE - #define sscratch mscratch - #define sstatus mstatus - #define scause mcause - #define sepc mepc - #define stvec_handler mtvec_handler -#endif - - li TESTNUM, 2 - .word 0 - j fail - - j pass - - TEST_PASSFAIL - -stvec_handler: - li t1, CAUSE_ILLEGAL_INSTRUCTION - csrr t0, scause - bne t0, t1, fail - csrr t0, sepc - addi t0, t0, 8 - csrw sepc, t0 - sret - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64si/ma_addr.S b/isa/rv64si/ma_addr.S deleted file mode 100644 index 525e028..0000000 --- a/isa/rv64si/ma_addr.S +++ /dev/null @@ -1,103 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# ma_addr.S -#----------------------------------------------------------------------------- -# -# Test misaligned ld/st trap. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64S -RVTEST_CODE_BEGIN - -#ifdef __MACHINE_MODE - #define sscratch mscratch - #define sstatus mstatus - #define scause mcause - #define sepc mepc - #define stvec_handler mtvec_handler -#endif - - la s0, stvec_handler - - # indicate it's a load test - li s1, 0 - -#define MISALIGNED_LDST_TEST(testnum, insn, base, offset) \ - li TESTNUM, testnum; \ - insn x0, offset(base); \ - j fail \ - - MISALIGNED_LDST_TEST(2, lh, s0, 1) - MISALIGNED_LDST_TEST(3, lhu, s0, 1) - MISALIGNED_LDST_TEST(4, lw, s0, 1) - MISALIGNED_LDST_TEST(5, lw, s0, 2) - MISALIGNED_LDST_TEST(6, lw, s0, 3) - -#ifdef __riscv64 - MISALIGNED_LDST_TEST(7, lwu, s0, 1) - MISALIGNED_LDST_TEST(8, lwu, s0, 2) - MISALIGNED_LDST_TEST(9, lwu, s0, 3) - - MISALIGNED_LDST_TEST(10, ld, s0, 1) - MISALIGNED_LDST_TEST(11, ld, s0, 2) - MISALIGNED_LDST_TEST(12, ld, s0, 3) - MISALIGNED_LDST_TEST(13, ld, s0, 4) - MISALIGNED_LDST_TEST(14, ld, s0, 5) - MISALIGNED_LDST_TEST(15, ld, s0, 6) - MISALIGNED_LDST_TEST(16, ld, s0, 7) -#endif - - # indicate it's a store test - li s1, 1 - - MISALIGNED_LDST_TEST(22, sh, s0, 1) - MISALIGNED_LDST_TEST(23, sw, s0, 1) - MISALIGNED_LDST_TEST(24, sw, s0, 2) - MISALIGNED_LDST_TEST(25, sw, s0, 3) - -#ifdef __riscv64 - MISALIGNED_LDST_TEST(26, sd, s0, 1) - MISALIGNED_LDST_TEST(27, sd, s0, 2) - MISALIGNED_LDST_TEST(28, sd, s0, 3) - MISALIGNED_LDST_TEST(29, sd, s0, 4) - MISALIGNED_LDST_TEST(30, sd, s0, 5) - MISALIGNED_LDST_TEST(31, sd, s0, 6) - MISALIGNED_LDST_TEST(32, sd, s0, 7) -#endif - - TEST_PASSFAIL - - .align 3 -stvec_handler: - bnez s1, test_store - -test_load: - li t1, CAUSE_MISALIGNED_LOAD - csrr t0, scause - bne t0, t1, fail - csrr t0, sepc - addi t0, t0, 8 - csrw sepc, t0 - sret - -test_store: - li t1, CAUSE_MISALIGNED_STORE - csrr t0, scause - bne t0, t1, fail - csrr t0, sepc - addi t0, t0, 8 - csrw sepc, t0 - sret - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END