From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 22 Apr 2022 14:23:39 +0000 (+0200)
Subject: Treat $anyseq as input from FST
X-Git-Tag: yosys-0.17~23^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4d80bc24c714f700519a2191a8929fe2136e45a3;p=yosys.git

Treat $anyseq as input from FST
---

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 345ca3494..5a36f87ec 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -804,6 +804,25 @@ struct SimInstance
 		return did_something;
 	}
 
+	void addAdditionalInputs(std::map<Wire*,fstHandle> &inputs)
+	{
+		for (auto cell : module->cells())
+		{
+			if (cell->type.in(ID($anyseq))) {
+				SigSpec sig_y= cell->getPort(ID::Y);
+				if (sig_y.is_wire()) {
+					Wire *wire = sig_y.as_wire();
+					fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
+					if (id==0)
+						log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str());
+					inputs[wire] = id;
+				}
+			}
+		}
+		for (auto child : children)
+			child.second->addAdditionalInputs(inputs);
+	}
+
 	void setState(dict<int, std::pair<SigBit,bool>> bits, std::string values)
 	{
 		for(auto bit : bits) {
@@ -1065,6 +1084,8 @@ struct SimWorker : SimShared
 			}
 		}
 
+		top->addAdditionalInputs(inputs);
+
 		uint64_t startCount = 0;
 		uint64_t stopCount = 0;
 		if (start_time==0) {