From: Wesley W. Terpstra Date: Thu, 2 Nov 2017 21:43:04 +0000 (-0700) Subject: freedom: bump submodules to their respective masters X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4eaac79ec25728cc76b161455cb1096589a5271c;p=freedom-sifive.git freedom: bump submodules to their respective masters --- diff --git a/common.mk b/common.mk index db05483..e23cbb7 100644 --- a/common.mk +++ b/common.mk @@ -72,11 +72,26 @@ endif .PHONY: romgen romgen: $(romgen) +f := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F +$(f): + echo $(VSRCS) > $@ + +bit := $(BUILD_DIR)/obj/$(MODEL).bit +$(bit): $(romgen) $(f) + cd $(BUILD_DIR); vivado \ + -nojournal -mode batch \ + -source $(fpga_common_script_dir)/vivado.tcl \ + -tclargs \ + -top-module "$(MODEL)" \ + -F "$(f)" \ + -ip-vivado-tcls "$(shell find '$(BUILD_DIR)' -name '*.vivado.tcl')" \ + -board "$(BOARD)" + + # Build .mcs -mcs := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).mcs -$(mcs): $(romgen) - VSRCS="$(VSRCS)" $(MAKE) -C $(FPGA_DIR) mcs - cp $(BUILD_DIR)/$(MODEL)/obj/system.mcs $@ +mcs := $(BUILD_DIR)/obj/$(MODEL).mcs +$(mcs): $(bit) + cd $(BUILD_DIR); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $< .PHONY: mcs mcs: $(mcs) diff --git a/fpga-shells b/fpga-shells index 2389e6e..ba7beb6 160000 --- a/fpga-shells +++ b/fpga-shells @@ -1 +1 @@ -Subproject commit 2389e6e95717caca782e7444422da16fef687188 +Subproject commit ba7beb676d55b73334bd4a85623e56c713a83773 diff --git a/rocket-chip b/rocket-chip index 82df766..7e75d63 160000 --- a/rocket-chip +++ b/rocket-chip @@ -1 +1 @@ -Subproject commit 82df766f4a5b1efb24b8659eb11c8b12c410a291 +Subproject commit 7e75d63ba6b4c1b50aaaf920e1c693ef6acf51d7 diff --git a/sifive-blocks b/sifive-blocks index f266b55..d1d2f47 160000 --- a/sifive-blocks +++ b/sifive-blocks @@ -1 +1 @@ -Subproject commit f266b55da92e42350be5704b4fe7d2a934e986ae +Subproject commit d1d2f47f609638c43546d4a9d0a4018c73dee4bb diff --git a/src/main/scala/everywhere/e300artydevkit/Platform.scala b/src/main/scala/everywhere/e300artydevkit/Platform.scala index a325333..be1789a 100644 --- a/src/main/scala/everywhere/e300artydevkit/Platform.scala +++ b/src/main/scala/everywhere/e300artydevkit/Platform.scala @@ -8,9 +8,9 @@ import freechips.rocketchip.coreplex._ import freechips.rocketchip.devices.debug._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.util.ResetCatchAndSync import freechips.rocketchip.system._ -import sifive.blocks.util.{ResetCatchAndSync} import sifive.blocks.devices.mockaon._ import sifive.blocks.devices.gpio._ import sifive.blocks.devices.jtag._ @@ -82,10 +82,10 @@ class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module { val spi_pins = sys.outer.spiParams.map { c => Wire(new SPIPins(() => PinGen(), c))} val i2c_pins = sys.outer.i2cParams.map { c => Wire(new I2CPins(() => PinGen()))} - (uart_pins zip sys_uart) map {case (p, r) => p.fromPort(r, clock = clock, reset = reset, syncStages = 0)} - (pwm_pins zip sys_pwm) map {case (p, r) => p.fromPort(r)} - (spi_pins zip sys_spi) map {case (p, r) => p.fromPort(r, clock = clock, reset = reset, syncStages = 0)} - (i2c_pins zip sys_i2c) map {case (p, r) => p.fromPort(r, clock = clock, reset = reset, syncStages = 0)} + (uart_pins zip sys_uart) map {case (p, r) => UARTPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)} + (pwm_pins zip sys_pwm) map {case (p, r) => PWMPinsFromPort(p, r) } + (spi_pins zip sys_spi) map {case (p, r) => SPIPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)} + (i2c_pins zip sys_i2c) map {case (p, r) => I2CPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)} //----------------------------------------------------------------------- // Default Pin connections before attaching pinmux @@ -157,14 +157,14 @@ class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module { //----------------------------------------------------------------------- // Result of Pin Mux - io.pins.gpio.fromPort(sys.gpio(0)) + GPIOPinsFromPort(io.pins.gpio, sys.gpio(0)) // Dedicated SPI Pads - io.pins.qspi.fromPort(sys.qspi(0), clock = sys.clock, reset = sys.reset, syncStages = 3) + SPIPinsFromPort(io.pins.qspi, sys.qspi(0), clock = sys.clock, reset = sys.reset, syncStages = 3) // JTAG Debug Interface val sjtag = sys.debug.systemjtag.get - io.pins.jtag.fromPort(sjtag.jtag) + JTAGPinsFromPort(io.pins.jtag, sjtag.jtag) sjtag.reset := io.jtag_reset sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) diff --git a/src/main/scala/unleashed/u500vc707devkit/Config.scala b/src/main/scala/unleashed/u500vc707devkit/Config.scala index a899e96..fd017bd 100644 --- a/src/main/scala/unleashed/u500vc707devkit/Config.scala +++ b/src/main/scala/unleashed/u500vc707devkit/Config.scala @@ -13,6 +13,8 @@ import sifive.blocks.devices.gpio._ import sifive.blocks.devices.spi._ import sifive.blocks.devices.uart._ +import sifive.fpgashells.devices.xilinx.xilinxvc707mig.{MemoryXilinxDDRKey,XilinxVC707MIGParams} + // Default FreedomUVC707Config class FreedomUVC707Config extends Config( new WithJtagDTM ++ @@ -40,7 +42,8 @@ class U500VC707DevKitConfig extends Config( new U500VC707DevKitPeripherals ++ new FreedomUVC707Config().alter((site,here,up) => { case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff))) - case PeripheryBusParams => up(PeripheryBusParams, site).copy(frequency = 50000000) // 50 MHz hperiphery + case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 50000000) // 50 MHz hperiphery + case MemoryXilinxDDRKey => XilinxVC707MIGParams(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB case DTSTimebase => BigInt(1000000) case ExtMem => up(ExtMem).copy(size = 0x40000000L) case JtagDTMKey => new JtagDTMConfig ( diff --git a/src/main/scala/unleashed/u500vc707devkit/FPGAChip.scala b/src/main/scala/unleashed/u500vc707devkit/FPGAChip.scala index b281bb8..9ac7667 100644 --- a/src/main/scala/unleashed/u500vc707devkit/FPGAChip.scala +++ b/src/main/scala/unleashed/u500vc707devkit/FPGAChip.scala @@ -10,7 +10,7 @@ import freechips.rocketchip.diplomacy._ import sifive.blocks.devices.gpio._ import sifive.blocks.devices.pinctrl.{BasePin} -import sifive.fpgashells.shell.xilinx.vc707shell.{VC707Shell} +import sifive.fpgashells.shell.xilinx.vc707shell._ import sifive.fpgashells.ip.xilinx.{IOBUF} //------------------------------------------------------------------------- @@ -27,7 +27,10 @@ object PinGen { // U500VC707DevKitFPGAChip //------------------------------------------------------------------------- -class U500VC707DevKitFPGAChip(implicit override val p: Parameters) extends VC707Shell { +class U500VC707DevKitFPGAChip(implicit override val p: Parameters) + extends VC707Shell + with HasPCIe + with HasDDR3 { //----------------------------------------------------------------------- // DUT @@ -55,7 +58,7 @@ class U500VC707DevKitFPGAChip(implicit override val p: Parameters) extends VC707 val gpioParams = p(PeripheryGPIOKey) val gpio_pins = Wire(new GPIOPins(() => PinGen(), gpioParams(0))) - gpio_pins.fromPort(dut.gpio(0)) + GPIOPinsFromPort(gpio_pins, dut.gpio(0)) gpio_pins.pins.foreach { _.i.ival := Bool(false) } gpio_pins.pins.zipWithIndex.foreach {