From: Luke Kenneth Casson Leighton Date: Sun, 27 Feb 2022 17:31:51 +0000 (+0000) Subject: add XLEN to issuer_verilog.py defaults to 64 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5bf5f6b2a8788ee21b9e309d858cac1eef5771fd;p=soc.git add XLEN to issuer_verilog.py defaults to 64 --- diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py index fdd43dbd..4198ae26 100644 --- a/src/soc/simple/issuer_verilog.py +++ b/src/soc/simple/issuer_verilog.py @@ -59,6 +59,8 @@ if __name__ == '__main__': parser.add_argument("--disable-svp64", dest='svp64', action="store_false", help="disable SVP64", default=False) + parser.add_argument("--xlen", default=64, type=int, + help="Set register width [default 64]") # create a module that's directly compatible as a drop-in replacement # in microwatt.v parser.add_argument("--microwatt-compat", dest='mwcompat', @@ -111,6 +113,8 @@ if __name__ == '__main__': imem_ifacetype=imem_ifacetype, addr_wid=64, mask_wid=8, + # pipeline and integer register file width + XLEN=args.xlen, # must leave at 64 reg_wid=64, # set to 32 for instruction-memory width=32 @@ -142,6 +146,7 @@ if __name__ == '__main__': print("use_pll", pspec.__dict__["use_pll"]) print("debug", pspec.__dict__["debug"]) print("SVP64", pspec.__dict__["svp64"]) + print("XLEN", pspec.__dict__["XLEN"]) print("Microwatt compatibility", pspec.__dict__["microwatt_compat"]) if args.mwcompat: