From: Luke Kenneth Casson Leighton Date: Sat, 20 Jun 2020 00:13:16 +0000 (+0100) Subject: fix nmigen imports X-Git-Tag: 24jan2021_ls180~10 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5cd5d13c36e18d04f084d48ff1e9d9a997a140e9;p=nmigen-soc.git fix nmigen imports --- diff --git a/nmigen_soc/csr/bus.py b/nmigen_soc/csr/bus.py index b865a01..4c6c6ac 100644 --- a/nmigen_soc/csr/bus.py +++ b/nmigen_soc/csr/bus.py @@ -1,5 +1,5 @@ import enum -from nmigen import * +from nmigen import Record, Elaboratable, Module, Signal, Mux from nmigen.utils import log2_int from ..memory import MemoryMap diff --git a/nmigen_soc/csr/wishbone.py b/nmigen_soc/csr/wishbone.py index a1767fc..54e3f49 100644 --- a/nmigen_soc/csr/wishbone.py +++ b/nmigen_soc/csr/wishbone.py @@ -1,4 +1,4 @@ -from nmigen import * +from nmigen import Elaboratable, Module, Signal, Cat from nmigen.utils import log2_int from . import Interface as CSRInterface diff --git a/nmigen_soc/scheduler.py b/nmigen_soc/scheduler.py index 9fffac5..29ab462 100644 --- a/nmigen_soc/scheduler.py +++ b/nmigen_soc/scheduler.py @@ -1,4 +1,4 @@ -from nmigen import * +from nmigen import Signal, Elaboratable, Module __all__ = ["RoundRobin"] diff --git a/nmigen_soc/test/test_csr_bus.py b/nmigen_soc/test/test_csr_bus.py index 3d530c1..e533318 100644 --- a/nmigen_soc/test/test_csr_bus.py +++ b/nmigen_soc/test/test_csr_bus.py @@ -1,9 +1,9 @@ # nmigen: UnusedElaboratable=no import unittest -from nmigen import * +from nmigen import Record, Module from nmigen.hdl.rec import Layout -from nmigen.back.pysim import * +from nmigen.back.pysim import Simulator, Fragment from ..csr.bus import * diff --git a/nmigen_soc/test/test_csr_wishbone.py b/nmigen_soc/test/test_csr_wishbone.py index 7c41cf2..adfa590 100644 --- a/nmigen_soc/test/test_csr_wishbone.py +++ b/nmigen_soc/test/test_csr_wishbone.py @@ -1,8 +1,8 @@ # nmigen: UnusedElaboratable=no import unittest -from nmigen import * -from nmigen.back.pysim import * +from nmigen import Elaboratable, Signal, Module +from nmigen.back.pysim import Simulator, Fragment from .. import csr from ..csr.wishbone import * diff --git a/nmigen_soc/test/test_wishbone_bus.py b/nmigen_soc/test/test_wishbone_bus.py index d93ea9d..1e63155 100644 --- a/nmigen_soc/test/test_wishbone_bus.py +++ b/nmigen_soc/test/test_wishbone_bus.py @@ -1,9 +1,9 @@ # nmigen: UnusedElaboratable=no import unittest -from nmigen import * -from nmigen.hdl.rec import * -from nmigen.back.pysim import * +from nmigen import Module, Record, Elaboratable +from nmigen.hdl.rec import Layout, DIR_FANOUT, DIR_FANIN +from nmigen.back.pysim import Simulator, Delay, Tick from ..wishbone import * diff --git a/nmigen_soc/wishbone/bus.py b/nmigen_soc/wishbone/bus.py index 580af84..37ce285 100644 --- a/nmigen_soc/wishbone/bus.py +++ b/nmigen_soc/wishbone/bus.py @@ -1,5 +1,5 @@ from enum import Enum -from nmigen import * +from nmigen import Record, Elaboratable, Module, Signal, Cat, Repl from nmigen.hdl.rec import Direction from nmigen.utils import log2_int diff --git a/nmigen_soc/wishbone/sram.py b/nmigen_soc/wishbone/sram.py index ac5f12b..f6734b2 100644 --- a/nmigen_soc/wishbone/sram.py +++ b/nmigen_soc/wishbone/sram.py @@ -1,5 +1,5 @@ -from nmigen import * -from nmigen.utils import * +from nmigen import Elaboratable, Memory, Module +from nmigen.utils import log2_int from .bus import Interface