From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 5 Apr 2021 11:05:49 +0000 (+0100)
Subject: sort out sdr and sdmmc OE pad drive, no longer one signal
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5ed734172992e2faca07318805780c8e650f14b1;p=libresoc-litex.git

sort out sdr and sdmmc OE pad drive, no longer one signal
---

diff --git a/libresoc/core.py b/libresoc/core.py
index d7ed1e7..ebf214e 100644
--- a/libresoc/core.py
+++ b/libresoc/core.py
@@ -118,11 +118,11 @@ def make_jtag_ioconn(res, pin, cpupads, iopads):
             pfx = ''
         elif fn.startswith('sd') and pin.startswith('data'):
             idx = int(pin[-1])
-            oe_idx = 0
+            oe_idx = idx
             pfx = pin[:-1]+"_"
         elif fn == 'sdr':
             idx = int(pin.split('_')[-1])
-            oe_idx = 0
+            oe_idx = idx
             pfx = pin.split('_')[0]+"_"
         else:
             idx = 0
diff --git a/libresoc/ls180.py b/libresoc/ls180.py
index c9d1028..ab8fb33 100644
--- a/libresoc/ls180.py
+++ b/libresoc/ls180.py
@@ -104,7 +104,7 @@ def io():
             Subsignal("cmd_oe",  Pins("J3"), Misc("PULLMODE=UP")),
             Subsignal("data_i", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
             Subsignal("data_o", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
-            Subsignal("data_oe", Pins("K2"), Misc("PULLMODE=UP")),
+            Subsignal("data_oe", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
             Misc("SLEWRATE=FAST"),
             IOStandard("LVCMOS33"),
         ),
@@ -121,7 +121,10 @@ def io():
             Subsignal("dq_o",    Pins(
                 "J16 L18 M18 N18 P18 T18 T17 U20",
                 "E19 D20 D19 C20 E18 F18 J18 J17")),
-            Subsignal("dq_oe",    Pins("J17")),
+            # ASIC pads all need an OE driver
+            Subsignal("dq_oe",    Pins(
+                "J16 L18 M18 N18 P18 T18 T17 U20",
+                "E19 D20 D19 C20 E18 F18 J18 J17")),
             Subsignal("we_n",  Pins("T20")),
             Subsignal("ras_n", Pins("R20")),
             Subsignal("cas_n", Pins("T19")),
diff --git a/ls180soc.py b/ls180soc.py
index 9821038..8e54d5e 100755
--- a/ls180soc.py
+++ b/ls180soc.py
@@ -142,8 +142,8 @@ class SDRPad(Module):
         _o = getattr(pad, "%s_o" % name)
         _oe = getattr(pad, "%s_oe" % name)
         _i = getattr(pad, "%s_i" % name)
-        self.specials += SDROutput(clk=clk, i=oe, o=_oe)
         for j in range(len(_o)):
+            self.specials += SDROutput(clk=clk, i=oe, o=_oe[j])
             self.specials += SDROutput(clk=clk, i=o[j], o=_o[j])
             self.specials += SDRInput(clk=clk, i=_i[j], o=i[j])