From: Jacob Lifshay Date: Fri, 15 Mar 2019 07:31:25 +0000 (-0700) Subject: convert into submodule X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6d483e32ea16d609ce53fc169d248d2e2873c641;p=nmigen-type-annotations.git convert into submodule --- 6d483e32ea16d609ce53fc169d248d2e2873c641 diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..ec31133 --- /dev/null +++ b/.gitignore @@ -0,0 +1,3 @@ +__pycache__ +.mypy_cache +*.pyc diff --git a/LICENSE.md b/LICENSE.md new file mode 100644 index 0000000..d55f608 --- /dev/null +++ b/LICENSE.md @@ -0,0 +1,503 @@ +### GNU LESSER GENERAL PUBLIC LICENSE + +Version 2.1, February 1999 + + Copyright (C) 1991, 1999 Free Software Foundation, Inc. + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + [This is the first released version of the Lesser GPL. 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If not, see . diff --git a/nmigen/__init__.pyi b/nmigen/__init__.pyi new file mode 100644 index 0000000..97420dc --- /dev/null +++ b/nmigen/__init__.pyi @@ -0,0 +1,11 @@ +# need "a as a" to work around mypy bug +from .hdl.dsl import Module as Module +from .hdl.ast import (Value as Value, + Const as Const, + C as C, + Mux as Mux, + Cat as Cat, + Repl as Repl, + Signal as Signal, + ClockSignal as ClockSignal, + ResetSignal as ResetSignal) diff --git a/nmigen/back/__init__.pyi b/nmigen/back/__init__.pyi new file mode 100644 index 0000000..e69de29 diff --git a/nmigen/back/pysim.pyi b/nmigen/back/pysim.pyi new file mode 100644 index 0000000..e797b5f --- /dev/null +++ b/nmigen/back/pysim.pyi @@ -0,0 +1,45 @@ +from ..hdl.ast import (Signal, Statement, Delay as Delay, + Tick as Tick, Passive as Passive, Assign, Value) +from typing import Any, Iterable, Generator, Union, Callable, Optional + +__all__ = ["Simulator", "Delay", "Tick", "Passive", "DeadlineError"] + +ProcessCommand = Union[Delay, Tick, Passive, Assign, Value] +ProcessGenerator = Generator[ProcessCommand, Union[int, None], None] +Process = Union[ProcessGenerator, Callable[[], ProcessGenerator]] + + +class Simulator: + def __init__(self, + fragment: Any, + vcd_file: Any = None, + gtkw_file: Any = None, + traces: Iterable[Signal] = ()): + ... + + def __enter__(self) -> 'Simulator': + ... + + def __exit__(self, *args: Any) -> None: + ... + + def add_process(self, process: Process) -> None: + ... + + def add_sync_process(self, process: Process) -> None: + ... + + def add_clock(self, + period: float, + phase: Optional[float] = None, + domain: Any = "sync") -> None: + ... + + def step(self, run_passive: bool = False) -> bool: + ... + + def run(self) -> None: + ... + + def run_until(self, deadline: float, run_passive: bool = False) -> bool: + ... diff --git a/nmigen/cli.py b/nmigen/cli.py new file mode 100644 index 0000000..9ade1c7 --- /dev/null +++ b/nmigen/cli.py @@ -0,0 +1,5 @@ +from typing import Any + + +def main(*args: Any, **kwargs: Any) -> None: + ... diff --git a/nmigen/hdl/__init__.pyi b/nmigen/hdl/__init__.pyi new file mode 100644 index 0000000..e69de29 diff --git a/nmigen/hdl/ast.pyi b/nmigen/hdl/ast.pyi new file mode 100644 index 0000000..97cfb10 --- /dev/null +++ b/nmigen/hdl/ast.pyi @@ -0,0 +1,260 @@ +from abc import ABCMeta, abstractmethod +from typing import Union, Tuple, Any, Iterable, Optional, Mapping +from collections.abc import MutableSequence + +__all__ = [ + "Value", "Const", "C", "AnyConst", "AnySeq", "Operator", "Mux", "Part", + "Slice", "Cat", "Repl", "Array", "ArrayProxy", "Sample", "Past", "Stable", + "Rose", "Fell", "Signal", "ClockSignal", "ResetSignal", "Statement", + "Assign", "Assert", "Assume", "Switch", "Delay", "Tick", "Passive", + "ValueKey", "ValueDict", "ValueSet", "SignalKey", "SignalDict", "SignalSet" +] + +ValueOrLiteral = Union[int, bool, 'Value'] +ShapeResult = Tuple[int, bool] + + +class Value(metaclass=ABCMeta): + def __invert__(self) -> 'Value': + ... + + def __neg__(self) -> 'Value': + ... + + def __add__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __radd__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __sub__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __rsub__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __mul__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __rmul__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __mod__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __rmod__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __div__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __rdiv__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __lshift__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __rlshift__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __rshift__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __rrshift__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __and__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __rand__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __xor__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __rxor__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __or__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __ror__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __eq__(self, other: Any) -> Any: + ... + + def __ne__(self, other: Any) -> Any: + ... + + def __lt__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __le__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __gt__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __ge__(self, other: ValueOrLiteral) -> 'Value': + ... + + def __len__(self) -> int: + ... + + def __getitem__(self, key: Union[slice, int]) -> 'Value': + ... + + def bool(self) -> 'Value': + ... + + def implies(premise: ValueOrLiteral, + conclusion: ValueOrLiteral) -> 'Value': + ... + + def part(self, offset: ValueOrLiteral, width: int) -> 'Value': + ... + + def eq(self, value: ValueOrLiteral) -> 'Assign': + ... + + @abstractmethod + def shape(self) -> ShapeResult: + ... + + +ShapeArgument = Union[int, Tuple[int, bool]] + + +class Const(Value): + nbits: int + signed: bool + + def __init__(self, value: int, + shape: Optional[ShapeArgument] = None) -> None: + ... + + def shape(self) -> ShapeResult: + ... + + +C = Const + + +def Mux(sel: ValueOrLiteral, + val1: ValueOrLiteral, + val0: ValueOrLiteral) -> Value: + ... + + +class Cat(Value): + def __init__(self, + *args: Union[ValueOrLiteral, + Iterable[ValueOrLiteral]]) -> None: + ... + + def shape(self) -> ShapeResult: + ... + + +class Repl(Value): + def __init__(self, + value: ValueOrLiteral, + count: int) -> None: + ... + + def shape(self) -> ShapeResult: + ... + + +class Signal(Value): + nbits: int + signed: bool + name: str + reset: int + reset_less: bool + attrs: dict + + def __init__(self, + shape: Optional[ShapeArgument] = None, + name: Optional[str] = None, + reset: int = 0, + reset_less: bool = False, + min: Optional[int] = None, max: Optional[int] = None, + attrs: Optional[dict] = None, + decoder: Any = None) -> None: + ... + + @classmethod + def like(cls, + other: ValueOrLiteral, + name: Optional[str] = None) -> 'Signal': + ... + + def shape(self) -> ShapeResult: + ... + + +class ClockSignal(Value): + def __init__(self, domain: str = "sync") -> None: + ... + + def shape(self) -> ShapeResult: + ... + + +class ResetSignal(Value): + def __init__(self, + domain: str = "sync", + allow_reset_less: bool = False) -> None: + ... + + def shape(self) -> ShapeResult: + ... + + +class Statement: + pass + + +StatementOrStatementList = Union[Iterable[Statement], Statement] + + +class Assign(Statement): + def __init__(self, lhs: ValueOrLiteral, rhs: ValueOrLiteral) -> None: + ... + + +class Property(Statement): + def __init__(self, test: ValueOrLiteral) -> None: + ... + + +class Assert(Property): + pass + + +class Assume(Property): + pass + + +class Switch(Statement): + def __init__(self, + test: ValueOrLiteral, + cases: Mapping[Union[bool, int, str], + StatementOrStatementList]) -> None: + ... + + +class Delay(Statement): + def __init__(self, interval: Optional[float]) -> None: + ... + + +class Tick(Statement): + def __init__(self, domain: Any = "sync"): + ... + + +class Passive(Property): + pass diff --git a/nmigen/hdl/dsl.pyi b/nmigen/hdl/dsl.pyi new file mode 100644 index 0000000..f7e6f70 --- /dev/null +++ b/nmigen/hdl/dsl.pyi @@ -0,0 +1,59 @@ +from .ast import Statement, ValueOrLiteral +from typing import Iterable, Union, Any +from contextlib import ContextDecorator + +__all__ = ["Module"] + + +class _ModuleBuilderProxy: + pass + + +Statements = Union[Statement, + Iterable[Statement]] + + +class _ModuleBuilderDomainExplicit(_ModuleBuilderProxy): + def __iadd__(self, + assigns: Statements) -> '_ModuleBuilderDomainExplicit': + ... + + +class _ModuleBuilderDomainImplicit(_ModuleBuilderProxy): + sync: _ModuleBuilderDomainExplicit + comb: _ModuleBuilderDomainExplicit + + +class _ModuleBuilderRoot: + domain: _ModuleBuilderDomainImplicit + d: _ModuleBuilderDomainImplicit + + +class _ValuelessContext: + def __enter__(self) -> None: + ... + + def __exit__(self, exc_type: Any, exc_value: Any, traceback: Any) -> bool: + ... + + +class Module(_ModuleBuilderRoot): + submodules: Any + + def If(self, cond: ValueOrLiteral) -> _ValuelessContext: + ... + + def Elif(self, cond: ValueOrLiteral) -> _ValuelessContext: + ... + + def Else(self) -> _ValuelessContext: + ... + + def Switch(self, test: ValueOrLiteral) -> _ValuelessContext: + ... + + def Case(self, value: Union[None, int, bool] = None) -> _ValuelessContext: + ... + + def elaborate(self, platform: Any) -> Any: + ... diff --git a/nmigen/tools.py b/nmigen/tools.py new file mode 100644 index 0000000..d5be0db --- /dev/null +++ b/nmigen/tools.py @@ -0,0 +1,6 @@ +def log2_int(n: int, need_pow2: bool = True) -> int: + ... + + +def bits_for(n: int, require_sign_bit: bool = False) -> int: + ...