From: Gabriel Somlo <gsomlo@gmail.com>
Date: Mon, 3 Aug 2020 18:32:26 +0000 (-0400)
Subject: interconnect/wishbone: increase WB address width to 31
X-Git-Tag: 24jan2021_ls180~36^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=70eae5cbf9faf9df5832f39cae455087aceed7b7;p=litex.git

interconnect/wishbone: increase WB address width to 31

This is needed to support memory regions up to 4GB in size (currently
limited to 2GB, or 0x8000_0000).

FIXME: CI complains about assertions re. axi_lite.address_width in
       relationship to len(wishbone.adr) and wishbone_adr_shift, which
       seems to be a problem on the 32bit (vexriscv?) CPU used for CI,
       but seems to work fine on Rocket.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>

foo
---

diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py
index d61edbea..235e14a3 100644
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@@ -35,7 +35,7 @@ _layout = [
 
 
 class Interface(Record):
-    def __init__(self, data_width=32, adr_width=30):
+    def __init__(self, data_width=32, adr_width=31):
         self.data_width = data_width
         self.adr_width  = adr_width
         Record.__init__(self, set_layout_parameters(_layout,