From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 7 Apr 2021 11:50:34 +0000 (+0100)
Subject: correct iverilog script errors
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=72c492a0a9dc6fc5a1f0d384d680a9200449c678;p=soc-cocotb-sim.git

correct iverilog script errors
---

diff --git a/ls180/pre_pnr/run_iverilog_wb_ls180.sh b/ls180/pre_pnr/run_iverilog_wb_ls180.sh
index 15ec6fe..db24552 100755
--- a/ls180/pre_pnr/run_iverilog_wb_ls180.sh
+++ b/ls180/pre_pnr/run_iverilog_wb_ls180.sh
@@ -1,6 +1,10 @@
 #!/bin/sh
 
+# create dummy memory files
+yes 0 | head -128 > mem_1.init 
+yes 0 | head -32 > mem_1.init 
 touch mem.init mem_1.init mem_2.init mem_3.init mem_4.init
+
 # Only run test in reset state as running CPU takes too much time to simulate
 make \
   SIM=icarus \
@@ -8,8 +12,8 @@ make \
   COCOTB_RESULTS_FILE=results_iverilog_ls180_wb.xml \
   COCOTB_HDL_TIMEUNIT=100ps \
   TESTCASE="wishbone_basic" \
-  SIM_BUILD=sim_build_iverilog_ls180 \
-  SIM_ARGS=--wave=test.ghw
+  MODULE="testwb" \
+  SIM_BUILD=sim_build_iverilog_wb_ls180