From: Andrew Waterman Date: Mon, 1 May 2017 21:44:42 +0000 (-0700) Subject: Set default entry point from ELF X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=75f2a05df9cdff6f3faba748065b3184b9f01b01;p=riscv-isa-sim.git Set default entry point from ELF --- diff --git a/riscv/sim.cc b/riscv/sim.cc index 59c4f0e..ebf94b6 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -45,8 +45,6 @@ sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc, clint.reset(new clint_t(procs)); bus.add_device(CLINT_BASE, clint.get()); - - make_dtb(); } sim_t::~sim_t() @@ -230,6 +228,7 @@ void sim_t::make_dtb() { const int reset_vec_size = 8; + start_pc = start_pc == reg_t(-1) ? get_entry_point() : start_pc; reg_t pc_delta = start_pc - DEFAULT_RSTVEC; reg_t pc_delta_hi = (pc_delta + 0x800U) & ~reg_t(0xfffU); reg_t pc_delta_lo = pc_delta - pc_delta_hi; @@ -325,6 +324,11 @@ char* sim_t::addr_to_mem(reg_t addr) { // htif +void sim_t::reset() +{ + make_dtb(); +} + void sim_t::idle() { target.switch_to(); diff --git a/riscv/sim.h b/riscv/sim.h index b2181ba..421f5c2 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -31,7 +31,7 @@ public: void set_histogram(bool value); void set_procs_debug(bool value); void set_gdbserver(gdbserver_t* gdbserver) { this->gdbserver = gdbserver; } - const char* get_dts() { return dts.c_str(); } + const char* get_dts() { if (dts.empty()) reset(); return dts.c_str(); } processor_t* get_core(size_t i) { return procs.at(i); } private: @@ -95,7 +95,7 @@ private: context_t* host; context_t target; - void reset() { } + void reset(); void idle(); void read_chunk(addr_t taddr, size_t len, void* dst); void write_chunk(addr_t taddr, size_t len, const void* src); diff --git a/spike_main/spike.cc b/spike_main/spike.cc index 5abdf24..d69d4bc 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -27,7 +27,7 @@ static void help() fprintf(stderr, " -h Print this help message\n"); fprintf(stderr, " -H Start halted, allowing a debugger to connect\n"); fprintf(stderr, " --isa= RISC-V ISA string [default %s]\n", DEFAULT_ISA); - fprintf(stderr, " --pc=
Set the initial program counter [default 0x80000000]\n"); + fprintf(stderr, " --pc=
Override ELF entry point\n"); fprintf(stderr, " --ic=:: Instantiate a cache model with S sets,\n"); fprintf(stderr, " --dc=:: W ways, and B-byte blocks (with S and\n"); fprintf(stderr, " --l2=:: B both powers of 2).\n"); @@ -75,7 +75,7 @@ int main(int argc, char** argv) bool log = false; bool dump_dts = false; size_t nprocs = 1; - reg_t start_pc = DRAM_BASE; + reg_t start_pc = reg_t(-1); std::vector> mems; std::unique_ptr ic; std::unique_ptr dc;