From: Megan Wachs Date: Tue, 13 Jun 2017 00:53:08 +0000 (-0700) Subject: GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7c118790cb89a74d8a67d8d1f78fe07b5a71038e;p=sifive-blocks.git GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful. --- diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala index e5cdd4e..bd77259 100644 --- a/src/main/scala/devices/spi/SPIPeriphery.scala +++ b/src/main/scala/devices/spi/SPIPeriphery.scala @@ -23,8 +23,8 @@ trait HasPeripherySPI extends HasSystemNetworks { trait HasPeripherySPIBundle { val spis: HeterogeneousBag[SPIPortIO] - def SPItoGPIOPins(dummy: Int = 1): Seq[SPIGPIOPort] = spis.map { s => - val pin = Module(new SPIGPIOPort(s.c)) + def SPItoGPIOPins(sync_stages: Int = 0): Seq[SPIGPIOPort] = spis.map { s => + val pin = Module(new SPIGPIOPort(s.c, sync_stages)) pin.io.spi <> s pin } diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala index a0e83ff..05c4a33 100644 --- a/src/main/scala/devices/uart/UARTPeriphery.scala +++ b/src/main/scala/devices/uart/UARTPeriphery.scala @@ -29,8 +29,8 @@ trait HasPeripheryUARTBundle { uarts.foreach { _.rxd := UInt(1) } } - def UARTtoGPIOPins(dummy: Int = 1): Seq[UARTGPIOPort] = uarts.map { u => - val pin = Module(new UARTGPIOPort) + def UARTtoGPIOPins(sync_stages: Int = 0): Seq[UARTGPIOPort] = uarts.map { u => + val pin = Module(new UARTGPIOPort(sync_stages)) pin.io.uart <> u pin }