From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 29 Apr 2019 04:13:00 +0000 (+0100)
Subject: shuffle imports
X-Git-Tag: ls180-24jan2020~1124
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7f58d174c4bffa5488f2b5b2ed6e4cd0e0fdbba4;p=ieee754fpu.git

shuffle imports
---

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index b1e808ae..7d08ccff 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -131,17 +131,15 @@
 
 from nmigen import Signal, Mux, Module, Elaboratable
 from nmigen.cli import verilog, rtlil
-from nmigen.lib.fifo import SyncFIFO, SyncFIFOBuffered
-from nmigen.hdl.ast import ArrayProxy
+from nmigen.lib.fifo import SyncFIFOBuffered
 from nmigen.hdl.rec import Record
 
 from queue import Queue
 import inspect
 
-import nmoperator
 from iocontrol import (PrevControl, NextControl, Object, RecordObject)
-from stageapi import (_spec, StageCls, Stage,
-                       StageChain, StageHelper)
+from stageapi import (_spec, StageCls, Stage, StageChain, StageHelper)
+import nmoperator
                       
 
 class RecordBasedStage(Stage):
@@ -729,8 +727,9 @@ class RegisterPipeline(UnbufferedPipeline):
 
 
 class FIFOControl(ControlBase):
-    """ FIFO Control.  Uses SyncFIFO to store data, coincidentally
+    """ FIFO Control.  Uses Queue to store data, coincidentally
         happens to have same valid/ready signalling as Stage API.
+        (TODO: remove use of SyncFIFOBuffered)
 
         data_i -> fifo.din -> FIFO -> fifo.dout -> data_o
     """