From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 25 Oct 2020 11:26:26 +0000 (+0000)
Subject: resolve issue in coriolis2 with passing nmigen expressions rather
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8416c08e7c47761c9c8db38124a1e08e85a1f55c;p=c4m-jtag.git

resolve issue in coriolis2 with passing nmigen expressions rather
than signals to a submodule
---

diff --git a/c4m/nmigen/jtag/tap.py b/c4m/nmigen/jtag/tap.py
index c090d3c..e9961d9 100755
--- a/c4m/nmigen/jtag/tap.py
+++ b/c4m/nmigen/jtag/tap.py
@@ -377,7 +377,11 @@ class TAP(Elaboratable):
         ir = irblock.ir
 
         # ID block
-        select_id = fsm.isdr & ((ir == cmd_idcode) | (ir == cmd_bypass))
+        select_id = Signal()
+        id_bypass = Signal()
+        m.d.comb += select_id.eq(fsm.isdr &
+                                 ((ir == cmd_idcode) | (ir == cmd_bypass)))
+        m.d.comb += id_bypass.eq(ir == cmd_bypass)
         m.submodules._idblock = idblock = _IDBypassBlock(
             manufacturer_id=self._manufacturer_id,
             part_number=self._part_number,
@@ -385,7 +389,7 @@ class TAP(Elaboratable):
             capture=(select_id & fsm.capture),
             shift=(select_id & fsm.shift),
             update=(select_id & fsm.update),
-            bypass=(ir == cmd_bypass),
+            bypass=id_bypass,
             name=self.name+"_id",
         )