From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 12 May 2019 14:23:01 +0000 (+0100)
Subject: add debug prints
X-Git-Tag: div_pipeline~2068
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=90e72563b5ac1dfba523686b4a85f7cd2354eaea;p=soc.git

add debug prints
---

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index d1a6d9c1..7796e700 100644
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -146,10 +146,10 @@ class Scoreboard(Elaboratable):
         for i, fu in enumerate(if_l):
             fn_issue_l.append(fu.issue_i)
             fn_busy_l.append(fu.busy_o)
-            m.d.comb += fu.issue_i.eq(issueunit.i.fn_issue_o[i])
-            m.d.comb += fu.dest_i.eq(self.int_dest_i)
-            m.d.comb += fu.src1_i.eq(self.int_src1_i)
-            m.d.comb += fu.src2_i.eq(self.int_src2_i)
+            m.d.sync += fu.issue_i.eq(issueunit.i.fn_issue_o[i])
+            m.d.sync += fu.dest_i.eq(self.int_dest_i)
+            m.d.sync += fu.src1_i.eq(self.int_src1_i)
+            m.d.sync += fu.src2_i.eq(self.int_src2_i)
             # XXX sync, so as to stop a simulation infinite loop
             m.d.sync += issueunit.i.busy_i[i].eq(fu.busy_o)
 
@@ -213,6 +213,7 @@ class Scoreboard(Elaboratable):
         #---------
         # Connect Register File(s)
         #---------
+        print ("intregdeps wen len", len(intregdeps.dest_rsel_o))
         m.d.comb += int_dest.wen.eq(intregdeps.dest_rsel_o)
         m.d.comb += int_src1.ren.eq(intregdeps.src1_rsel_o)
         m.d.comb += int_src2.ren.eq(intregdeps.src2_rsel_o)
@@ -345,7 +346,7 @@ def scoreboard_sim(dut, alusim):
             break
             if dest not in [src1, src2]:
                 break
-        src1 = 3
+        src1 = 4
         src2 = 1
         dest = 1
 
@@ -372,6 +373,7 @@ def scoreboard_sim(dut, alusim):
     yield
     yield
     yield from alusim.check(dut)
+    yield from alusim.dump(dut)
 
 
 def explore_groups(dut):
diff --git a/src/scoreboard/fu_reg_matrix.py b/src/scoreboard/fu_reg_matrix.py
index f15d19f5..94d30600 100644
--- a/src/scoreboard/fu_reg_matrix.py
+++ b/src/scoreboard/fu_reg_matrix.py
@@ -111,6 +111,8 @@ class FURegDepMatrix(Elaboratable):
         m.d.comb += self.rd_src1_pend_o.eq(Cat(*rd_src1_pend))
         m.d.comb += self.rd_src2_pend_o.eq(Cat(*rd_src2_pend))
 
+        print ("wr pend len", len(wr_pend))
+
         # ---
         # connect Reg Selection vector
         # ---
@@ -137,12 +139,14 @@ class FURegDepMatrix(Elaboratable):
             dest_rsel.append(rsv.dest_rsel_o)
             src1_rsel.append(rsv.src1_rsel_o)
             src2_rsel.append(rsv.src2_rsel_o)
+            print ("dest_rsel_rsv len", len(rsv.dest_rsel_o))
 
         # ... and output them from this module (horizontal, width=REGs)
         m.d.comb += self.dest_rsel_o.eq(Cat(*dest_rsel))
         m.d.comb += self.src1_rsel_o.eq(Cat(*src1_rsel))
         m.d.comb += self.src2_rsel_o.eq(Cat(*src2_rsel))
 
+        print ("dest rsel len", len(dest_rsel), self.dest_rsel_o)
         # ---
         # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
         # ---