From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 15 May 2019 15:23:43 +0000 (+0100)
Subject: write-after-read hazard working
X-Git-Tag: div_pipeline~2041
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=967aa20ad7d20e59f3fad05ac78e6d8f76b8f242;p=soc.git

write-after-read hazard working
---

diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py
index 2edf6587..3c97c19a 100644
--- a/src/experiment/compalu.py
+++ b/src/experiment/compalu.py
@@ -54,7 +54,7 @@ class ComputationUnitNoDelay(Elaboratable):
         m.d.comb += self.busy_o.eq(opc_l.q) # busy out
 
         with m.If(self.go_rd_i):
-            m.d.sync += self.counter.eq(1)
+            m.d.sync += self.counter.eq(2)
         with m.If(self.counter > 0):
             m.d.sync += self.counter.eq(self.counter - 1)
         with m.If(self.counter == 1):
diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py
index b0318b90..5d6edf63 100644
--- a/src/experiment/cscore.py
+++ b/src/experiment/cscore.py
@@ -331,17 +331,16 @@ def scoreboard_sim(dut, alusim):
         yield from int_instr(dut, alusim, op, src1, src2, dest)
         yield from print_reg(dut, [3,4,5])
         yield
-        yield from print_reg(dut, [3,4,5])
-        for i in range(len(dut.int_insn_i)):
-            yield dut.int_insn_i[i].eq(0)
-        yield
-        yield
-        yield
         while True:
             issue_o = yield dut.issue_o
             if issue_o:
                 break
+            print ("busy",)
+            yield from print_reg(dut, [3,4,5])
             yield
+        yield from print_reg(dut, [3,4,5])
+        for i in range(len(dut.int_insn_i)):
+            yield dut.int_insn_i[i].eq(0)
 
 
     yield
diff --git a/src/scoreboard/fn_unit.py b/src/scoreboard/fn_unit.py
index 3edabbde..a4eff476 100644
--- a/src/scoreboard/fn_unit.py
+++ b/src/scoreboard/fn_unit.py
@@ -141,9 +141,9 @@ class FnUnit(Elaboratable):
         src1_r = Signal(max=self.reg_width, reset_less=True)
         src2_r = Signal(max=self.reg_width, reset_less=True)
         # XXX latch based on *issue* rather than !latch (as in book)
-        latchregister(m, self.dest_i, dest_r, self.issue_i) #wr_l.qn)
-        latchregister(m, self.src1_i, src1_r, self.issue_i) #wr_l.qn)
-        latchregister(m, self.src2_i, src2_r, self.issue_i) #wr_l.qn)
+        latchregister(m, self.dest_i, dest_r, wr_l.qn)
+        latchregister(m, self.src1_i, src1_r, wr_l.qn)
+        latchregister(m, self.src2_i, src2_r, wr_l.qn)
 
         # dest decoder (use dest reg as input): write-pending out
         m.d.comb += dest_d.i.eq(dest_r)
@@ -165,7 +165,7 @@ class FnUnit(Elaboratable):
         ro = Signal(reset_less=True)
         m.d.comb += g_rd.eq(self.g_wr_pend_i & self.rd_pend_o)
         m.d.comb += ro.eq(~g_rd.bool())
-        m.d.comb += self.readable_o.eq(ro & rd_l.q)
+        m.d.comb += self.readable_o.eq(ro & wr_l.q)
 
         # writable output signal
         g_wr_v = Signal(self.reg_width, reset_less=True)