From: Luke Kenneth Casson Leighton Date: Thu, 1 Oct 2020 17:15:54 +0000 (+0100) Subject: must not delay ack to wb request in SRAM X-Git-Tag: 24jan2021_ls180 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=HEAD;p=nmigen-soc.git must not delay ack to wb request in SRAM --- diff --git a/nmigen_soc/wishbone/sram.py b/nmigen_soc/wishbone/sram.py index 22b0efd..1575e6a 100644 --- a/nmigen_soc/wishbone/sram.py +++ b/nmigen_soc/wishbone/sram.py @@ -95,16 +95,9 @@ class SRAM(Elaboratable): with m.If(wen): m.d.comb += wrport.en.eq(self.bus.sel) - # generate ack + # generate ack (no "pipeline" mode here) m.d.sync += self.bus.ack.eq(0) - with m.If(self.bus.cyc & self.bus.stb & ~self.bus.ack): - if False: # test which deliberately delays response - counter = Signal(3) - m.d.sync += counter.eq(counter + 1) - with m.If(counter == 7): - m.d.sync += self.bus.ack.eq(1) - m.d.sync += counter.eq(0) - else: - m.d.sync += self.bus.ack.eq(1) + with m.If(self.bus.cyc & self.bus.stb): + m.d.sync += self.bus.ack.eq(1) return m