From: Andrew Waterman Date: Thu, 3 Mar 2016 06:34:19 +0000 (-0800) Subject: Make JALR test sensible in RISC-V, rather than SMIPS X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a0a3ae4841308010c6437e0f47467af97a140cda;p=riscv-tests.git Make JALR test sensible in RISC-V, rather than SMIPS --- diff --git a/isa/rv32ui/jalr.S b/isa/rv32ui/jalr.S index ebe3731..59f6425 100644 --- a/isa/rv32ui/jalr.S +++ b/isa/rv32ui/jalr.S @@ -1,88 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# jalr.S -#----------------------------------------------------------------------------- -# -# Test jalr instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Test 2: Basic test - #------------------------------------------------------------- - -test_2: - li TESTNUM, 2 - li x31, 0 - la x2, target_2 - -linkaddr_2: - jalr x19, x2, 0 - nop - nop - - j fail - -target_2: - la x1, linkaddr_2 - addi x1, x1, 4 - bne x1, x19, fail - - #------------------------------------------------------------- - # Test 3: Check r0 target and that r31 is not modified - #------------------------------------------------------------- - -test_3: - li TESTNUM, 3 - li x31, 0 - la x3, target_3 - -linkaddr_3: - jalr x0, x3, 0 - nop - - j fail - -target_3: - bne x31, x0, fail - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_JALR_SRC1_BYPASS( 4, 0, jalr ); - TEST_JALR_SRC1_BYPASS( 5, 1, jalr ); - TEST_JALR_SRC1_BYPASS( 6, 2, jalr ); - - #------------------------------------------------------------- - # Test delay slot instructions not executed nor bypassed - #------------------------------------------------------------- - - TEST_CASE( 7, x1, 4, \ - li x1, 1; \ - la x2, 1f; - jalr x19, x2, -4; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ -1: addi x1, x1, 1; \ - addi x1, x1, 1; \ - ) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/jalr.S" diff --git a/isa/rv64ui/jalr.S b/isa/rv64ui/jalr.S index c821165..210973e 100644 --- a/isa/rv64ui/jalr.S +++ b/isa/rv64ui/jalr.S @@ -19,38 +19,16 @@ RVTEST_CODE_BEGIN test_2: li TESTNUM, 2 - li x31, 0 - la x2, target_2 + li t0, 0 + la t1, target_2 + jalr t0, t1, 0 linkaddr_2: - jalr x19, x2, 0 - nop - nop - j fail target_2: - la x1, linkaddr_2 - addi x1, x1, 4 - bne x1, x19, fail - - #------------------------------------------------------------- - # Test 3: Check r0 target and that r31 is not modified - #------------------------------------------------------------- - -test_3: - li TESTNUM, 3 - li x31, 0 - la x3, target_3 - -linkaddr_3: - jalr x0, x3, 0 - nop - - j fail - -target_3: - bne x31, x0, fail + la t1, linkaddr_2 + bne t0, t1, fail #------------------------------------------------------------- # Bypassing tests @@ -64,16 +42,16 @@ target_3: # Test delay slot instructions not executed nor bypassed #------------------------------------------------------------- - TEST_CASE( 7, x1, 4, \ - li x1, 1; \ - la x2, 1f; - jalr x19, x2, -4; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ -1: addi x1, x1, 1; \ - addi x1, x1, 1; \ + TEST_CASE( 7, t0, 4, \ + li t0, 1; \ + la t1, 1f; \ + jr t1, -4; \ + addi t0, t0, 1; \ + addi t0, t0, 1; \ + addi t0, t0, 1; \ + addi t0, t0, 1; \ +1: addi t0, t0, 1; \ + addi t0, t0, 1; \ ) TEST_PASSFAIL