From: Luke Kenneth Casson Leighton Date: Mon, 22 Mar 2021 12:40:35 +0000 (+0000) Subject: make sure non-svp64-mode works X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a24012a91b3527c3d44bea32eb730356e2e8e357;p=soc.git make sure non-svp64-mode works --- diff --git a/Makefile b/Makefile index 28b8f38b..0ab0037e 100644 --- a/Makefile +++ b/Makefile @@ -38,7 +38,7 @@ testgpio_run_sim: ls180_verilog: python3 src/soc/simple/issuer_verilog.py \ --debug=jtag --enable-core --enable-pll \ - --enable-xics --enable-sram4x4kblock + --enable-xics --enable-sram4x4kblock --disable-svp64 src/soc/litex/florent/libresoc/libresoc.v test: install diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 0efbc95b..482d3640 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -353,7 +353,8 @@ class TestIssuerInternal(Elaboratable): # here or maybe even in INSN_READ state, if svp64_mode # detected, in order to trigger - and wait for - the # predicate reading. - pmode = pdecode2.rm_dec.predmode + if self.svp64_en: + pmode = pdecode2.rm_dec.predmode """ if pmode != SVP64PredMode.ALWAYS.value: fire predicate loading FSM and wait before @@ -556,7 +557,10 @@ class TestIssuerInternal(Elaboratable): comb += self.insn_done.eq(1) m.next = "ISSUE_START" with m.Else(): - m.next = "PRED_START" # start fetching the predicate + if self.svp64_en: + m.next = "PRED_START" # start fetching predicate + else: + m.next = "INSN_EXECUTE" # skip predication with m.State("PRED_START"): comb += pred_insn_valid_i.eq(1) # tell fetch_pred to start @@ -581,8 +585,9 @@ class TestIssuerInternal(Elaboratable): with m.If(is_svp64_mode): - pred_src_zero = pdecode2.rm_dec.pred_sz - pred_dst_zero = pdecode2.rm_dec.pred_dz + if self.svp64_en: + pred_src_zero = pdecode2.rm_dec.pred_sz + pred_dst_zero = pdecode2.rm_dec.pred_dz """ if not pred_src_zero: @@ -900,9 +905,10 @@ class TestIssuerInternal(Elaboratable): exec_insn_valid_i, exec_insn_ready_o, exec_pc_valid_o, exec_pc_ready_i) - self.fetch_predicate_fsm(m, - pred_insn_valid_i, pred_insn_ready_o, - pred_mask_valid_o, pred_mask_ready_i) + if self.svp64_en: + self.fetch_predicate_fsm(m, + pred_insn_valid_i, pred_insn_ready_o, + pred_mask_valid_o, pred_mask_ready_i) self.execute_fsm(m, core, pc_changed, sv_changed, exec_insn_valid_i, exec_insn_ready_o,