From: Michael Nolan Date: Sat, 29 Feb 2020 19:32:18 +0000 (-0500) Subject: Move decoder.py to power_major_decoder.py X-Git-Tag: div_pipeline~1814 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a4f7613fd1b07ef070252822bc6be0b030fedf96;p=soc.git Move decoder.py to power_major_decoder.py --- diff --git a/.gitignore b/.gitignore index 54746077..c5947d94 100644 --- a/.gitignore +++ b/.gitignore @@ -8,3 +8,4 @@ Waveforms !**/Waveforms/.gitkeep *.egg-info *.il +**/*.gtkw diff --git a/src/decoder/decoder.py b/src/decoder/decoder.py deleted file mode 100644 index 6aa96d61..00000000 --- a/src/decoder/decoder.py +++ /dev/null @@ -1,54 +0,0 @@ -from nmigen import Module, Elaboratable, Signal -import csv -import os -from enum import Enum, unique - -@unique -class Function(Enum): - ALU = 0 - LDST = 1 - -@unique -class InternalOp(Enum): - OP_ADD = 0 - OP_AND = 1 - OP_B = 2 - OP_BC = 3 - OP_CMP = 4 - OP_LOAD = 5 - OP_MUL_L64 = 6 - OP_OR = 7 - OP_RLC = 8 - OP_STORE = 9 - OP_TDI = 10 - OP_XOR = 11 - -def get_csv(name): - file_dir = os.path.dirname(os.path.realpath(__file__)) - with open(os.path.join(file_dir, name)) as csvfile: - reader = csv.DictReader(csvfile) - return list(reader) - -major_opcodes = get_csv("major.csv") - -class PowerDecoder(Elaboratable): - def __init__(self): - self.opcode_in = Signal(6, reset_less=True) - - self.function_unit = Signal(Function, reset_less=True) - self.internal_op = Signal(InternalOp, reset_less=True) - def elaborate(self, platform): - m = Module() - comb = m.d.comb - - with m.Switch(self.opcode_in): - for row in major_opcodes: - opcode = int(row['opcode']) - with m.Case(opcode): - comb += self.function_unit.eq(Function[row['unit']]) - comb += self.internal_op.eq(InternalOp[row['internal op']]) - return m - - - - diff --git a/src/decoder/power_major_decoder.py b/src/decoder/power_major_decoder.py new file mode 100644 index 00000000..c71fa155 --- /dev/null +++ b/src/decoder/power_major_decoder.py @@ -0,0 +1,54 @@ +from nmigen import Module, Elaboratable, Signal +import csv +import os +from enum import Enum, unique + +@unique +class Function(Enum): + ALU = 0 + LDST = 1 + +@unique +class InternalOp(Enum): + OP_ADD = 0 + OP_AND = 1 + OP_B = 2 + OP_BC = 3 + OP_CMP = 4 + OP_LOAD = 5 + OP_MUL_L64 = 6 + OP_OR = 7 + OP_RLC = 8 + OP_STORE = 9 + OP_TDI = 10 + OP_XOR = 11 + +def get_csv(name): + file_dir = os.path.dirname(os.path.realpath(__file__)) + with open(os.path.join(file_dir, name)) as csvfile: + reader = csv.DictReader(csvfile) + return list(reader) + +major_opcodes = get_csv("major.csv") + +class PowerMajorDecoder(Elaboratable): + def __init__(self): + self.opcode_in = Signal(6, reset_less=True) + + self.function_unit = Signal(Function, reset_less=True) + self.internal_op = Signal(InternalOp, reset_less=True) + def elaborate(self, platform): + m = Module() + comb = m.d.comb + + with m.Switch(self.opcode_in): + for row in major_opcodes: + opcode = int(row['opcode']) + with m.Case(opcode): + comb += self.function_unit.eq(Function[row['unit']]) + comb += self.internal_op.eq(InternalOp[row['internal op']]) + return m + + + + diff --git a/src/decoder/test/test_decoder.py b/src/decoder/test/test_decoder.py deleted file mode 100644 index 222dedab..00000000 --- a/src/decoder/test/test_decoder.py +++ /dev/null @@ -1,47 +0,0 @@ -from nmigen import Module, Elaboratable, Signal -from nmigen.back.pysim import Simulator, Delay, Settle -from nmigen.test.utils import FHDLTestCase -from nmigen.cli import rtlil -import sys -import unittest -sys.path.append("../") -from decoder import PowerDecoder, Function, InternalOp, major_opcodes - -class DecoderTestCase(FHDLTestCase): - def test_function_unit(self): - m = Module() - comb = m.d.comb - opcode = Signal(6) - function_unit = Signal(Function) - internal_op = Signal(InternalOp) - - m.submodules.dut = dut = PowerDecoder() - comb += [dut.opcode_in.eq(opcode), - function_unit.eq(dut.function_unit), - internal_op.eq(dut.internal_op)] - - sim = Simulator(m) - def process(): - for row in major_opcodes: - yield opcode.eq(int(row['opcode'])) - yield Delay(1e-6) - result = yield function_unit - expected = Function[row['unit']].value - self.assertEqual(expected, result) - - result = yield internal_op - expected = InternalOp[row['internal op']].value - self.assertEqual(expected, result) - sim.add_process(process) - with sim.write_vcd("test.vcd", "test.gtkw", traces=[opcode, function_unit, internal_op]): - sim.run() - - def test_ilang(self): - dut = PowerDecoder() - vl = rtlil.convert(dut, ports=[dut.opcode_in, dut.function_unit]) - with open("power_decoder.il", "w") as f: - f.write(vl) - -if __name__ == "__main__": - unittest.main() - diff --git a/src/decoder/test/test_power_major_decoder.py b/src/decoder/test/test_power_major_decoder.py new file mode 100644 index 00000000..05d9b13c --- /dev/null +++ b/src/decoder/test/test_power_major_decoder.py @@ -0,0 +1,48 @@ +from nmigen import Module, Elaboratable, Signal +from nmigen.back.pysim import Simulator, Delay, Settle +from nmigen.test.utils import FHDLTestCase +from nmigen.cli import rtlil +import sys +import unittest +sys.path.append("../") +from power_major_decoder import (PowerMajorDecoder, Function, + InternalOp, major_opcodes) + +class DecoderTestCase(FHDLTestCase): + def test_function_unit(self): + m = Module() + comb = m.d.comb + opcode = Signal(6) + function_unit = Signal(Function) + internal_op = Signal(InternalOp) + + m.submodules.dut = dut = PowerMajorDecoder() + comb += [dut.opcode_in.eq(opcode), + function_unit.eq(dut.function_unit), + internal_op.eq(dut.internal_op)] + + sim = Simulator(m) + def process(): + for row in major_opcodes: + yield opcode.eq(int(row['opcode'])) + yield Delay(1e-6) + result = yield function_unit + expected = Function[row['unit']].value + self.assertEqual(expected, result) + + result = yield internal_op + expected = InternalOp[row['internal op']].value + self.assertEqual(expected, result) + sim.add_process(process) + with sim.write_vcd("test.vcd", "test.gtkw", traces=[opcode, function_unit, internal_op]): + sim.run() + + def test_ilang(self): + dut = PowerMajorDecoder() + vl = rtlil.convert(dut, ports=[dut.opcode_in, dut.function_unit]) + with open("power_major_decoder.il", "w") as f: + f.write(vl) + +if __name__ == "__main__": + unittest.main() +