From: Luke Kenneth Casson Leighton Date: Tue, 19 Mar 2019 05:15:04 +0000 (+0000) Subject: output less-than test to ilang X-Git-Tag: ls180-24jan2020~1632 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a58c598b6635baafd0afdb3f467bc72d0a59161b;p=ieee754fpu.git output less-than test to ilang --- diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py index b84a6604..e32e2d32 100644 --- a/src/add/test_buf_pipe.py +++ b/src/add/test_buf_pipe.py @@ -1,5 +1,7 @@ from nmigen import Module, Signal, Mux from nmigen.compat.sim import run_simulation +from nmigen.cli import verilog, rtlil + from example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd from example_buf_pipe import ExampleCombPipe, CombPipe from example_buf_pipe import PrevControl, NextControl @@ -346,3 +348,10 @@ if __name__ == '__main__': test = Test5(dut, test6_resultfn) run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltcomb6.vcd") + ports = [dut.p.i_valid, dut.n.i_ready, + dut.n.o_valid, dut.p.o_ready] + \ + list(dut.p.i_data) + [dut.n.o_data] + vl = rtlil.convert(dut, ports=ports) + with open("test_ltcomb_pipe.il", "w") as f: + f.write(vl) +