From: Jacob Lifshay Date: Fri, 17 Dec 2021 01:37:26 +0000 (-0800) Subject: move do_sim and hash_256 to separate module X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a8614226c8db483291d188e1f0bde17c9544cba0;p=nmutil.git move do_sim and hash_256 to separate module --- diff --git a/src/nmutil/sim_util.py b/src/nmutil/sim_util.py new file mode 100644 index 0000000..643c32e --- /dev/null +++ b/src/nmutil/sim_util.py @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: LGPL-3-or-later +# See Notices.txt for copyright information + +from contextlib import contextmanager +from hashlib import sha256 +from nmutil.get_test_path import get_test_path +from nmigen.sim import Simulator + + +def hash_256(v): + return int.from_bytes( + sha256(bytes(v, encoding='utf-8')).digest(), + byteorder='little' + ) + + +@contextmanager +def do_sim(test_case, dut, traces=()): + sim = Simulator(dut) + path = get_test_path(test_case, "sim_test_out") + path.parent.mkdir(parents=True, exist_ok=True) + vcd_path = path.with_suffix(".vcd") + gtkw_path = path.with_suffix(".gtkw") + with sim.write_vcd(vcd_path.open("wt", encoding="utf-8"), + gtkw_path.open("wt", encoding="utf-8"), + traces=traces): + yield sim diff --git a/src/nmutil/test/test_lut.py b/src/nmutil/test/test_lut.py index 00e3ea4..b30c4b7 100644 --- a/src/nmutil/test/test_lut.py +++ b/src/nmutil/test/test_lut.py @@ -1,35 +1,13 @@ # SPDX-License-Identifier: LGPL-3-or-later # See Notices.txt for copyright information -from contextlib import contextmanager import unittest -from hashlib import sha256 from nmigen.hdl.ast import AnyConst, Assert, Signal from nmigen.hdl.dsl import Module from nmutil.formaltest import FHDLTestCase -from nmutil.get_test_path import get_test_path from nmutil.lut import BitwiseMux, BitwiseLut, TreeBitwiseLut -from nmigen.sim import Simulator, Delay - - -@contextmanager -def do_sim(test_case, dut, traces=()): - sim = Simulator(dut) - path = get_test_path(test_case, "sim_test_out") - path.parent.mkdir(parents=True, exist_ok=True) - vcd_path = path.with_suffix(".vcd") - gtkw_path = path.with_suffix(".gtkw") - with sim.write_vcd(vcd_path.open("wt", encoding="utf-8"), - gtkw_path.open("wt", encoding="utf-8"), - traces=traces): - yield sim - - -def hash_256(v): - return int.from_bytes( - sha256(bytes(v, encoding='utf-8')).digest(), - byteorder='little' - ) +from nmigen.sim import Delay +from nmutil.sim_util import do_sim, hash_256 class TestBitwiseMux(FHDLTestCase):