From: Luke Kenneth Casson Leighton Date: Mon, 4 Apr 2022 19:13:41 +0000 (+0100) Subject: allow direction-setting on each of dq0-3 in Tercel QSPI X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ab8dd1234f3999b5720ca9e0fbdb1412f9f2d806;p=soc.git allow direction-setting on each of dq0-3 in Tercel QSPI --- diff --git a/src/soc/bus/tercel.py b/src/soc/bus/tercel.py index 3e71a3bf..f04f356a 100644 --- a/src/soc/bus/tercel.py +++ b/src/soc/bus/tercel.py @@ -166,11 +166,13 @@ class Tercel(Elaboratable): m.submodules['tercel_%d' % self.idx] = tercel if pins is not None: - comb += pins.dq.o.eq(self.dq_out) - comb += pins.dq.oe.eq(self.dq_direction) - comb += pins.dq.o_clk.eq(ClockSignal()) - comb += self.dq_in.eq(pins.dq.i) - comb += pins.dq.i_clk.eq(ClockSignal()) + for i in range(4): + pad = getattr(pins, "dq%d" % i) + comb += pad.o.eq(self.dq_out[i]) + comb += pad.oe.eq(self.dq_direction[i]) + comb += pad.o_clk.eq(ClockSignal()) + comb += self.dq_in[i].eq(pad.i) + comb += pad.i_clk.eq(ClockSignal()) # XXX invert handled by SPIFlashResource comb += pins.cs_n.eq(self.cs_n_out) # ECP5 needs special handling for the SPI clock, sigh.