From: Harry Ho <hh@m-labs.hk>
Date: Wed, 8 Jan 2020 06:39:43 +0000 (+0800)
Subject: wishbone: optimise SRAM addr_width
X-Git-Tag: 24jan2021_ls180~23
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ad14cd097e58f8d73b53c13c36bdbe3299f249ad;p=nmigen-soc.git

wishbone: optimise SRAM addr_width
---

diff --git a/nmigen_soc/wishbone/sram.py b/nmigen_soc/wishbone/sram.py
index 3ee165e..b72687d 100644
--- a/nmigen_soc/wishbone/sram.py
+++ b/nmigen_soc/wishbone/sram.py
@@ -25,7 +25,7 @@ class SRAM(Elaboratable):
         if not read_only:
             self._memdepth += self.memory.depth
         if bus is None:
-            bus = Interface(addr_width=bits_for(self._memdepth),
+            bus = Interface(addr_width=max(0, log2_int(self._memdepth, need_pow2=False)),
                             data_width=self.memory.width,
                             granularity=granularity,
                             features=features,