From: Luke Kenneth Casson Leighton Date: Thu, 1 Apr 2021 12:10:00 +0000 (+0100) Subject: add no pll ls180 build X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=af28b2d17c0f9e038935867e96f750ecec61aeb7;p=soc.git add no pll ls180 build --- diff --git a/Makefile b/Makefile index abb446dd..8412997a 100644 --- a/Makefile +++ b/Makefile @@ -36,6 +36,12 @@ testgpio_run_sim: python3 src/soc/litex/florent/sim.py --cpu=libresoc \ --variant=standardjtagtestgpio +ls180_verilog_nopll: + python3 src/soc/simple/issuer_verilog.py \ + --debug=jtag --enable-core --disable-pll \ + --enable-xics --disable-svp64 \ + src/soc/litex/florent/libresoc/libresoc.v + ls180_verilog: python3 src/soc/simple/issuer_verilog.py \ --debug=jtag --enable-core --enable-pll \