From: Megan Wachs Date: Mon, 8 Aug 2016 19:24:44 +0000 (-0700) Subject: By default debug=False X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b00a402f5d921fda37a7e5e59b8d4c566467f0a4;p=riscv-tests.git By default debug=False --- diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 0693518..9d6f781 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -593,7 +593,7 @@ class FreedomE300SimTarget(Target): instruction_hardware_breakpoint_count = 2 def server(self): - sim = testlib.VcsSim(simv=parsed.run, debug=True) + sim = testlib.VcsSim(simv=parsed.run, debug=False) x = testlib.Openocd(cmd=parsed.cmd, config="targets/%s/openocd.cfg" % self.name, otherProcess = sim) @@ -610,7 +610,7 @@ class FreedomU500SimTarget(Target): instruction_hardware_breakpoint_count = 2 def server(self): - sim = testlib.VcsSim(simv=parsed.run, debug=True) + sim = testlib.VcsSim(simv=parsed.run, debug=False) x = testlib.Openocd(cmd=parsed.cmd, config="targets/%s/openocd.cfg" % self.name, otherProcess = sim)