From: Andrew Waterman Date: Tue, 20 Mar 2012 06:40:38 +0000 (-0700) Subject: make NaN behavior consistent with hardfloat X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b282d6e8c016680e101f50e6b88ea3e505484912;p=riscv-isa-sim.git make NaN behavior consistent with hardfloat --- diff --git a/riscv/insns/fadd_d.h b/riscv/insns/fadd_d.h index 48c76a7..dcc6413 100644 --- a/riscv/insns/fadd_d.h +++ b/riscv/insns/fadd_d.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -FRD = f64_add(FRS1, FRS2); +FRD = f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2); set_fp_exceptions; diff --git a/riscv/insns/fadd_s.h b/riscv/insns/fadd_s.h index 2fd5429..952d1a7 100644 --- a/riscv/insns/fadd_s.h +++ b/riscv/insns/fadd_s.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -FRD = f32_add(FRS1, FRS2); +FRD = f32_mulAdd(FRS1, 0x3f800000, FRS2); set_fp_exceptions; diff --git a/riscv/insns/fmul_d.h b/riscv/insns/fmul_d.h index a8adedd..a1462d3 100644 --- a/riscv/insns/fmul_d.h +++ b/riscv/insns/fmul_d.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -FRD = f64_mul(FRS1, FRS2); +FRD = f64_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint64_t)INT64_MIN); set_fp_exceptions; diff --git a/riscv/insns/fmul_s.h b/riscv/insns/fmul_s.h index 6475578..a954c3d 100644 --- a/riscv/insns/fmul_s.h +++ b/riscv/insns/fmul_s.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -FRD = f32_mul(FRS1, FRS2); +FRD = f32_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint32_t)INT32_MIN); set_fp_exceptions; diff --git a/riscv/insns/fnmadd_d.h b/riscv/insns/fnmadd_d.h index 1e2ee27..9529aeb 100644 --- a/riscv/insns/fnmadd_d.h +++ b/riscv/insns/fnmadd_d.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -FRD = f64_mulAdd(FRS1, FRS2, FRS3) ^ (uint64_t)INT64_MIN; +FRD = f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3 ^ (uint64_t)INT64_MIN); set_fp_exceptions; diff --git a/riscv/insns/fnmadd_s.h b/riscv/insns/fnmadd_s.h index 78abb78..2052b93 100644 --- a/riscv/insns/fnmadd_s.h +++ b/riscv/insns/fnmadd_s.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -FRD = f32_mulAdd(FRS1, FRS2, FRS3) ^ (uint32_t)INT32_MIN; +FRD = f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3 ^ (uint32_t)INT32_MIN); set_fp_exceptions; diff --git a/riscv/insns/fnmsub_d.h b/riscv/insns/fnmsub_d.h index ae643a5..31a5b39 100644 --- a/riscv/insns/fnmsub_d.h +++ b/riscv/insns/fnmsub_d.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN; +FRD = f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3); set_fp_exceptions; diff --git a/riscv/insns/fnmsub_s.h b/riscv/insns/fnmsub_s.h index cbb70ba..811a35a 100644 --- a/riscv/insns/fnmsub_s.h +++ b/riscv/insns/fnmsub_s.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN; +FRD = f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3); set_fp_exceptions; diff --git a/riscv/insns/fsub_d.h b/riscv/insns/fsub_d.h index e25eebb..fcabe0e 100644 --- a/riscv/insns/fsub_d.h +++ b/riscv/insns/fsub_d.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -FRD = f64_sub(FRS1, FRS2); +FRD = f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2 ^ (uint64_t)INT64_MIN); set_fp_exceptions; diff --git a/riscv/insns/fsub_s.h b/riscv/insns/fsub_s.h index 6c64d04..1ff72d2 100644 --- a/riscv/insns/fsub_s.h +++ b/riscv/insns/fsub_s.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -FRD = f32_sub(FRS1, FRS2); +FRD = f32_mulAdd(FRS1, 0x3f800000, FRS2 ^ (uint32_t)INT32_MIN); set_fp_exceptions; diff --git a/softfloat/f64_to_i64.c b/softfloat/f64_to_i64.c index 89663ee..676e944 100755 --- a/softfloat/f64_to_i64.c +++ b/softfloat/f64_to_i64.c @@ -29,7 +29,7 @@ int_fast64_t f64_to_i64( float64_t a, int_fast8_t roundingMode, bool exact ) return ! sign || ( ( exp == 0x7FF ) - && ( sig != UINT64_C( 0x0010000000000000 ) ) ) + && fracF64UI( uiA ) ) ? INT64_C( 0x7FFFFFFFFFFFFFFF ) : - INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1; }