From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 22 Mar 2019 11:38:01 +0000 (+0000)
Subject: rename CombPipe to Pipeline
X-Git-Tag: ls180-24jan2020~1526
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b47fa0f247c5afff0b9aba8be3025abfe9d912ea;p=ieee754fpu.git

rename CombPipe to Pipeline
---

diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py
index 929bb465..b7d38b0f 100644
--- a/src/add/example_buf_pipe.py
+++ b/src/add/example_buf_pipe.py
@@ -389,7 +389,7 @@ class ExampleBufPipe(BufferedPipeline):
         BufferedPipeline.__init__(self, ExampleStage)
 
 
-class CombPipe(PipelineBase):
+class Pipeline(PipelineBase):
     """ A simple pipeline stage with single-clock synchronisation
         and two-way valid/ready synchronised signalling.  The stage
         requires a combinatorial block.
@@ -459,12 +459,12 @@ class CombPipe(PipelineBase):
         return m
 
 
-class ExampleCombPipe(CombPipe):
+class ExamplePipeline(Pipeline):
     """ an example of how to use the combinatorial pipeline.
     """
 
     def __init__(self):
-        CombPipe.__init__(self, ExampleStage)
+        Pipeline.__init__(self, ExampleStage)
 
 
 if __name__ == '__main__':
@@ -473,7 +473,7 @@ if __name__ == '__main__':
     with open("test_bufpipe.il", "w") as f:
         f.write(vl)
 
-    dut = ExampleCombPipe()
+    dut = ExamplePipeline()
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_combpipe.il", "w") as f:
         f.write(vl)
diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index bde24cca..e037a51e 100644
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -4,7 +4,7 @@ from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
 from example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd
-from example_buf_pipe import ExampleCombPipe, CombPipe, ExampleStageCls
+from example_buf_pipe import ExamplePipeline, Pipeline, ExampleStageCls
 from example_buf_pipe import PrevControl, NextControl, BufferedPipeline
 from example_buf_pipe import StageChain
 
@@ -362,13 +362,13 @@ class LTStageDerived(SetLessThan):
         return self.output
 
 
-class ExampleLTCombPipe(CombPipe):
+class ExampleLTPipeline(Pipeline):
     """ an example of how to use the combinatorial pipeline.
     """
 
     def __init__(self):
         stage = LTStage()
-        CombPipe.__init__(self, stage)
+        Pipeline.__init__(self, stage)
 
 
 class ExampleLTBufferedPipeDerived(BufferedPipeline):
@@ -407,13 +407,13 @@ class ExampleAddRecordStage:
                 'src2': i.src2 + 1}
 
 
-class ExampleAddRecordPipe(CombPipe):
+class ExampleAddRecordPipe(Pipeline):
     """ an example of how to use the combinatorial pipeline.
     """
 
     def __init__(self):
         stage = ExampleAddRecordStage()
-        CombPipe.__init__(self, stage)
+        Pipeline.__init__(self, stage)
 
 
 def test7_resultfn(o_data, expected, i, o):
@@ -507,7 +507,7 @@ if __name__ == '__main__':
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe3.vcd")
 
     print ("test 3.5")
-    dut = ExampleCombPipe()
+    dut = ExamplePipeline()
     test = Test3(dut, test3_resultfn)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_combpipe3.vcd")
 
@@ -521,7 +521,7 @@ if __name__ == '__main__':
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe5.vcd")
 
     print ("test 6")
-    dut = ExampleLTCombPipe()
+    dut = ExampleLTPipeline()
     test = Test5(dut, test6_resultfn)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltcomb6.vcd")