From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 16 Apr 2021 22:47:15 +0000 (+0100)
Subject: single-cycle mode fix on wb "wen" signal, must hold fully until ACKed
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b69ecc9d4fb3a0926a617cb9c669b87808b55fdd;p=c4m-jtag.git

single-cycle mode fix on wb "wen" signal, must hold fully until ACKed
---

diff --git a/c4m/nmigen/jtag/tap.py b/c4m/nmigen/jtag/tap.py
index 1cdc833..12902ee 100755
--- a/c4m/nmigen/jtag/tap.py
+++ b/c4m/nmigen/jtag/tap.py
@@ -789,6 +789,7 @@ class TAP(Elaboratable):
                 if hasattr(wb, "stall"):
                     m.d.comb += wb.stb.eq(fsm.ongoing("READ") |
                                           fsm.ongoing("WRITEREAD"))
+                    m.d.comb += wb.we.eq(fsm.ongoing("WRITEREAD"))
                 else:
                     # non-stall is single-cycle (litex), must assert stb
                     # until ack is sent
@@ -796,7 +797,6 @@ class TAP(Elaboratable):
                                           fsm.ongoing("WRITEREAD") |
                                           fsm.ongoing("READACK") |
                                           fsm.ongoing("WRITEREADACK"))
-                m.d.comb += [
-                    wb.cyc.eq(~fsm.ongoing("IDLE")),
-                    wb.we.eq(fsm.ongoing("WRITEREAD")),
-                ]
+                    m.d.comb += wb.we.eq(fsm.ongoing("WRITEREAD") |
+                                         fsm.ongoing("WRITEREADACK"))
+                m.d.comb += wb.cyc.eq(~fsm.ongoing("IDLE"))