From: Henry Styles Date: Tue, 25 Apr 2017 17:15:00 +0000 (-0700) Subject: Use _chisel3 analog for MIG inout X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b882d6da934b8a6f0f1780c0cedfaf54ba7701c8;p=sifive-blocks.git Use _chisel3 analog for MIG inout --- diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala index 526305a..0ea057f 100644 --- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala +++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala @@ -2,28 +2,21 @@ package sifive.blocks.devices.xilinxvc707mig import Chisel._ +import chisel3.experimental.{Analog,attach} import config._ import diplomacy._ import uncore.tilelink2._ import uncore.axi4._ import rocketchip._ -import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGUnidirectionalIOClocksReset, VC707MIGUnidirectionalIODDR, vc707mig} +import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig} trait HasXilinxVC707MIGParameters { } -class XilinxVC707MIGPads extends Bundle with VC707MIGUnidirectionalIODDR { - val _inout_ddr3_dq = Bits(OUTPUT,64) - val _inout_ddr3_dqs_n = Bits(OUTPUT,8) - val _inout_ddr3_dqs_p = Bits(OUTPUT,8) -} +class XilinxVC707MIGPads extends Bundle with VC707MIGIODDR -class XilinxVC707MIGIO extends Bundle with VC707MIGUnidirectionalIODDR - with VC707MIGUnidirectionalIOClocksReset { - val _inout_ddr3_dq = Bits(OUTPUT,64) - val _inout_ddr3_dqs_n = Bits(OUTPUT,8) - val _inout_ddr3_dqs_p = Bits(OUTPUT,8) -} +class XilinxVC707MIGIO extends Bundle with VC707MIGIODDR + with VC707MIGIOClocksReset class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC707MIGParameters { val device = new MemoryDevice @@ -58,9 +51,9 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC //pins to top level //inouts - io.port._inout_ddr3_dq := blackbox.io.ddr3_dq - io.port._inout_ddr3_dqs_n := blackbox.io.ddr3_dqs_n - io.port._inout_ddr3_dqs_p := blackbox.io.ddr3_dqs_p + attach(io.port.ddr3_dq,blackbox.io.ddr3_dq) + attach(io.port.ddr3_dqs_n,blackbox.io.ddr3_dqs_n) + attach(io.port.ddr3_dqs_p,blackbox.io.ddr3_dqs_p) //outputs io.port.ddr3_addr := blackbox.io.ddr3_addr diff --git a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala index 923956b..6f281ec 100644 --- a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala +++ b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala @@ -2,15 +2,14 @@ package sifive.blocks.ip.xilinx.vc707mig import Chisel._ +import chisel3.experimental.{Analog,attach} import config._ import junctions._ // IP VLNV: xilinx.com:customize_ip:vc707mig:1.0 // Black Box -// Signals named _exactly_ as per MIG generated verilog -trait VC707MIGUnidirectionalIODDR extends Bundle { - //outputs +trait VC707MIGIODDR extends Bundle { val ddr3_addr = Bits(OUTPUT,14) val ddr3_ba = Bits(OUTPUT,3) val ddr3_ras_n = Bool(OUTPUT) @@ -23,10 +22,14 @@ trait VC707MIGUnidirectionalIODDR extends Bundle { val ddr3_cs_n = Bits(OUTPUT,1) val ddr3_dm = Bits(OUTPUT,8) val ddr3_odt = Bits(OUTPUT,1) + + val ddr3_dq = Analog(64.W) + val ddr3_dqs_n = Analog(8.W) + val ddr3_dqs_p = Analog(8.W) } //reused directly in io bundle for sifive.blocks.devices.xilinxvc707mig -trait VC707MIGUnidirectionalIOClocksReset extends Bundle { +trait VC707MIGIOClocksReset extends Bundle { //inputs //differential system clocks val sys_clk_n = Bool(INPUT) @@ -45,14 +48,8 @@ trait VC707MIGUnidirectionalIOClocksReset extends Bundle { //turn off linter: blackbox name must match verilog module class vc707mig(implicit val p:Parameters) extends BlackBox { - val io = new Bundle with VC707MIGUnidirectionalIODDR - with VC707MIGUnidirectionalIOClocksReset { - // bidirectional signals on blackbox interface - // defined here as an output so "__inout" signal name does not have to be used - // verilog does not check the - val ddr3_dq = Bits(OUTPUT,64) - val ddr3_dqs_n = Bits(OUTPUT,8) - val ddr3_dqs_p = Bits(OUTPUT,8) + val io = new Bundle with VC707MIGIODDR + with VC707MIGIOClocksReset { // User interface signals val app_sr_req = Bool(INPUT) val app_ref_req = Bool(INPUT)