From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 22 Apr 2022 15:20:17 +0000 (+0200)
Subject: Match $anyseq input if connected to public wire
X-Git-Tag: yosys-0.17~23^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bbfdea2f8a200f40f82600b48afddb66e5f0e1d2;p=yosys.git

Match $anyseq input if connected to public wire
---

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 5a36f87ec..5f795e94c 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -809,13 +809,19 @@ struct SimInstance
 		for (auto cell : module->cells())
 		{
 			if (cell->type.in(ID($anyseq))) {
-				SigSpec sig_y= cell->getPort(ID::Y);
+				SigSpec sig_y = sigmap(cell->getPort(ID::Y));
 				if (sig_y.is_wire()) {
-					Wire *wire = sig_y.as_wire();
-					fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
-					if (id==0)
-						log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str());
-					inputs[wire] = id;
+					bool found = false;
+					for(auto &item : fst_handles) {
+						if (item.second==0) continue; // Ignore signals not found
+						if (sig_y == sigmap(item.first)) {
+							inputs[sig_y.as_wire()] = item.second;
+							found = true;
+							break;
+						}
+					}
+					if (!found)
+						log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(sig_y.as_wire()->name)).c_str());
 				}
 			}
 		}