From: Wesley W. Terpstra Date: Sat, 13 May 2017 06:07:10 +0000 (-0700) Subject: vc707mig: use an external ibuf X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c4c158963c6f1532cb7ca35166d9078c5a04f55f;p=sifive-blocks.git vc707mig: use an external ibuf This makes it possible to also drive a PLL of our own from the crystal. --- diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala index 58d14f4..f6ae153 100644 --- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala +++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala @@ -77,9 +77,8 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC io.port.ddr3_odt := blackbox.io.ddr3_odt //inputs - //differential system clock - blackbox.io.sys_clk_n := io.port.sys_clk_n - blackbox.io.sys_clk_p := io.port.sys_clk_p + //NO_BUFFER clock + blackbox.io.sys_clk_i := io.port.sys_clk_i //user interface signals val axi_async = axi4.bundleIn(0) diff --git a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala index 6f281ec..d7b522f 100644 --- a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala +++ b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala @@ -31,9 +31,8 @@ trait VC707MIGIODDR extends Bundle { //reused directly in io bundle for sifive.blocks.devices.xilinxvc707mig trait VC707MIGIOClocksReset extends Bundle { //inputs - //differential system clocks - val sys_clk_n = Bool(INPUT) - val sys_clk_p = Bool(INPUT) + //"NO_BUFFER" clock source (must be connected to IBUF outside of IP) + val sys_clk_i = Bool(INPUT) //user interface signals val ui_clk = Clock(OUTPUT) val ui_clk_sync_rst = Bool(OUTPUT)