From: Megan Wachs <megan@sifive.com>
Date: Wed, 22 Mar 2017 00:51:28 +0000 (-0700)
Subject: TLSPI: address parameter must now be a sequence.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c6d7326669d851e6d154a33822821f77703e1c3c;hp=77246eaada9532ff5f7dad1d4e293ac8b054236a;p=sifive-blocks.git

TLSPI: address parameter must now be a sequence.
---

diff --git a/src/main/scala/devices/spi/TLSPI.scala b/src/main/scala/devices/spi/TLSPI.scala
index b20b524..5c5b9bf 100644
--- a/src/main/scala/devices/spi/TLSPI.scala
+++ b/src/main/scala/devices/spi/TLSPI.scala
@@ -110,7 +110,7 @@ class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLS
 abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) extends LazyModule {
   require(isPow2(c.rSize))
   val device = new SimpleDevice("spi", Seq("sifive,spi0"))
-  val rnode = TLRegisterNode(address = AddressSet(c.rAddress, c.rSize-1), device = device, beatBytes = w)
+  val rnode = TLRegisterNode(address = Seq(AddressSet(c.rAddress, c.rSize-1)), device = device, beatBytes = w)
   val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int))
 }