From: Jacob Lifshay Date: Mon, 6 Apr 2020 19:00:27 +0000 (-0700) Subject: Merge branch 'fix-tests' X-Git-Tag: div_pipeline~1440 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd4cbabf64842fbdb3a276ba8134b9dcd43da4c8;p=soc.git Merge branch 'fix-tests' --- cd4cbabf64842fbdb3a276ba8134b9dcd43da4c8 diff --cc src/soc/decoder/isa/test_caller.py index 0e9c1131,55dcc673..0a26c816 --- a/src/soc/decoder/isa/test_caller.py +++ b/src/soc/decoder/isa/test_caller.py @@@ -79,17 -79,7 +79,17 @@@ class DecoderTestCase(FHDLTestCase) print(sim.gpr(1)) self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64)) + def test_addpcis(self): + lst = ["addpcis 1, 0x1", + "addpcis 2, 0x1", + "addpcis 3, 0x1"] + with Program(lst) as program: - sim = self.run_test_program(program) ++ sim = self.run_tst_program(program) + self.assertEqual(sim.gpr(1), SelectableInt(0x10004, 64)) + self.assertEqual(sim.gpr(2), SelectableInt(0x10008, 64)) + self.assertEqual(sim.gpr(3), SelectableInt(0x1000c, 64)) + - def run_test_program(self, prog, initial_regs=[0] * 32): + def run_tst_program(self, prog, initial_regs=[0] * 32): simulator = self.run_tst(prog, initial_regs) simulator.gpr.dump() return simulator