From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 20 Feb 2019 04:54:41 +0000 (+0000)
Subject: latch into FPNumIn within module
X-Git-Tag: ls180-24jan2020~1857
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cf05c428f2442b1432e2dfdc32f93c5db66cba44;p=ieee754fpu.git

latch into FPNumIn within module
---

diff --git a/src/add/fpbase.py b/src/add/fpbase.py
index 592a3f72..962dfcf6 100644
--- a/src/add/fpbase.py
+++ b/src/add/fpbase.py
@@ -177,12 +177,18 @@ class FPNumIn(FPNumBase):
         (m[-1]) is effectively a carry-overflow.  The other three are
         guard (m[2]), round (m[1]), and sticky (m[0])
     """
-    def __init__(self, width, m_extra=True):
+    def __init__(self, op, width, m_extra=True):
         FPNumBase.__init__(self, width, m_extra)
+        self.latch_in = Signal()
+        self.op = op
 
     def elaborate(self, platform):
         m = FPNumBase.elaborate(self, platform)
 
+        m.d.comb += self.latch_in.eq(self.op.ack & self.op.stb)
+        with m.If(self.latch_in):
+            m.d.sync += self.decode(self.v)
+
         return m
 
     def decode(self, v):
@@ -291,7 +297,7 @@ class FPBase:
         with m.If((op.ack) & (op.stb)):
             m.next = next_state
             m.d.sync += [
-                v.decode(op.v),
+                # op is latched in from FPNumIn class on same ack/stb
                 op.ack.eq(0)
             ]
         with m.Else():
diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index b1e633eb..184aa91e 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -25,14 +25,17 @@ class FPADD(FPBase):
         m = Module()
 
         # Latches
-        a = FPNumIn(self.width)
-        b = FPNumIn(self.width)
+        a = FPNumIn(self.in_a, self.width)
+        b = FPNumIn(self.in_b, self.width)
         z = FPNumOut(self.width, False)
 
         m.submodules.fpnum_a = a
         m.submodules.fpnum_b = b
         m.submodules.fpnum_z = z
 
+        m.d.comb += a.v.eq(self.in_a.v)
+        m.d.comb += b.v.eq(self.in_b.v)
+
         w = z.m_width + 4
         tot = Signal(w, reset_less=True) # sticky/round/guard, {mantissa} result, 1 overflow