From: Luke Kenneth Casson Leighton Date: Fri, 18 Feb 2022 20:50:22 +0000 (+0000) Subject: add blockram style to regfile Memory X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d868a8ed77ebad2c1df449cb70349c6c6eea2c20;p=soc.git add blockram style to regfile Memory --- diff --git a/src/soc/regfile/regfile.py b/src/soc/regfile/regfile.py index e1274b4b..07cee2dd 100644 --- a/src/soc/regfile/regfile.py +++ b/src/soc/regfile/regfile.py @@ -199,7 +199,8 @@ class RegFileMem(Elaboratable): self.fwd_bus_mode = fwd_bus_mode self.synced = synced self.width, self.depth = width, depth - self.memory = Memory(width=width, depth=depth) + self.memory = Memory(width=width, depth=depth, + attrs={'syn_ramstyle': "block_ram"}) self._rdports = {} self._wrports = {}